Method for manufacturing wiring board, and wiring board

Patent metadata

Field	Value
Publication number	US-2021204409-A1
Application number	US-202017122021-A
Country	US
Kind code	A1
Filing date	Dec 15, 2020
Priority date	Dec 26, 2019
Publication date	Jul 1, 2021
Grant date	—

Abstract

A method for manufacturing a wiring board is capable of forming a metal layer included in a wiring layer to have an even thickness. The method includes preparing a conductive first underlayer on a surface of a substrate; a conductive second underlayer on a surface of the first underlayer; and a seed layer on a surface of the second underlayer and containing metal. The method disposes a solid electrolyte membrane between an anode and the seed layer as a cathode; applies voltage between the anode and the first underlayer to form a metal layer on the surface of the seed layer; removes an exposed portion of the second underlayer without the seed layer from the substrate; and removes an exposed portion of the first underlayer without the seed layer from the substrate. The first underlayer is a material having a higher electrical conductivity than that of the second underlayer.

First claim

What is claimed is:

1 . A method for manufacturing a wiring board including an insulating substrate, and a wiring layer disposed on a surface of the insulating substrate and having a predetermined wiring pattern, the method comprising:
preparing a substrate with seed-layer, the substrate with seed-layer including: a conductive first underlayer on the surface of the insulating substrate; a conductive second underlayer on the surface of the first underlayer; and a seed layer on the surface of the second underlayer, the seed layer having a predetermined pattern corresponding to the wiring pattern and containing metal; disposing a solid electrolyte membrane between an anode and the seed layer as a cathode, pressing the solid electrolyte membrane against at least the seed layer, and applying voltage between the anode and the first underlayer to reduce metal ions contained in the solid electrolyte membrane and so form a metal layer on the surface of the seed layer; and removing an exposed portion of the second underlayer without the seed layer from the insulating substrate, and after removal of the second underlayer, removing an exposed portion of the first underlayer without the seed layer from the insulating substrate to form the wiring layer. wherein the first underlayer is formed of material having a higher electrical conductivity than that of the second underlayer.

2 . The method for manufacturing the wiring board according to claim 1 , wherein the first underlayer has a volume resistivity within the range from 1.60B10 −8 WXm to 5.00B10 −7 WXm.

3 . The method for manufacturing the wiring board according to claim 2 , wherein the second underlayer has a volume resistivity within the range from 1.0B10 −6 WXm to 3.7B10 −6 WXm.

4 . The method for manufacturing the wiring board according to any claim 1 , wherein the second underlayer contains oxide in at least a surface of a portion of the second underlayer, on which the seed layer is not formed, and the first underlayer is formed of material having a higher electrical conductivity than that of a portion of the second underlayer not containing the oxide.

5 . The method for manufacturing the wiring board according to claim 1 , wherein the first underlayer has a 10-point average roughness Rz of 0.5 mm or less.

6 . A wiring board comprising an insulating substrate, and a wiring layer disposed on a surface of the insulating substrate and having a predetermined wiring pattern,
the wiring layer including: a conductive first underlayer disposed on the surface of the insulating substrate; a conductive second underlayer disposed on a surface of the first underlayer; a seed layer disposed on a surface of the second underlayer and containing metal; and a metal layer disposed on a surface of the seed layer, wherein the first underlayer is formed of material having a higher electrical conductivity than that of the second underlayer.

7 . The wiring board according to claim 6 , wherein the first underlayer has a volume resistivity within the range from 1.60B10 −8 WXm to 5.00B10 −7 WXm.

8 . The wiring board according to claim 7 , wherein the second underlayer has a volume resistivity within the range from 1.0B10 −6 WXm to 3.7B10 −6 WXm.

Assignees

• Toyota Motor Co Ltd

Inventors

• Kondoh Haruki
• Mori Rentaro
• Kuroda Keiji
• Yanagimoto Hiroshi
• Okamoto Kazuaki

Classifications

• C23C18/28

  Sensitising or activating · CPC title

• H05K2203/0716

  Metallic plating catalysts, e.g. for direct electroplating of through holes; Sensitising or activating metallic plating catalysts · CPC title

• H05K2203/0713

  Plating poison, e.g. for selective plating or for preventing plating on resist · CPC title

• H05K3/1208

  Pretreatment of the circuit board, e.g. modifying wetting properties; Patterning by using affinity patterns (providing shape patterns H05K3/1258; adhesion treatments H05K3/38) · CPC title

• H05K3/12

  using {thick film techniques, e.g.} printing techniques to apply the conductive material {or similar techniques for applying conductive paste or ink patterns} · CPC title