Iterative Estimation Hardware

Patent metadata

Field	Value
Publication number	US-2020201629-A1
Application number	US-201916725378-A
Country	US
Kind code	A1
Filing date	Dec 23, 2019
Priority date	Dec 21, 2018
Publication date	Jun 25, 2020
Grant date	—

Abstract

A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by

1


/



d
i

.

The hardware logic comprises a plurality of multipliers and adders arranged to implement a m th -order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.

First claim

What is claimed is:

1 . A function estimation hardware logic unit for use in an arithmetic logic unit of a processor, the function estimation hardware logic arranged to calculate, in hardware logic, an improved estimate, x n+1 , for a function of an input value, d, wherein the function is

1


/



d
i

,

and the hardware logic comprising:
a first input arranged to receive the input value, d;
a second input arranged to receive an estimate, x n , for the function of the input value; and
an output arranged to output the improved estimate, x n+1 , for the function of the input value; and
a combination of multiplier and addition hardware blocks configured in hardware circuitry to implement an m th -order polynomial to determine the improved estimate, x n+1 , with m th order convergence, wherein the m th -order polynomial can be expressed as:

f

i
,
m



(

x
,
d

)

=

x

n
+
1

=

x
n



(

∏

k
=
1

m
-
1





(

1
+

1
ki

)

)



∑

j
=
0

m
-
1





(

m
-
1

j

)



(

-

dx
n
i

)

j

ji
+
1

where i and m are natural numbers, wherein m>2, wherein

(

m
-
1

j

)

is a binomial coefficient and is equal to zero if j>(m−1).

2 . The function estimation hardware logic unit according to claim 1 , wherein m is not equal to a power of two.

3 . The function estimation hardware logic unit according to claim 1 , wherein m=3.

4 . The function estimation hardware logic unit according to claim 1 , wherein m and i have any combination of values except for m=3 and i=2.

5 . The function estimation hardware logic unit according to claim 1 , wherein m>3.

6 . The function estimation hardware logic unit according to claim 5 , wherein m=4.

7 . The function estimation hardware logic unit according to claim 1 , wherein i=1, such that the m th -order polynomial can be expressed as:

x

n
+
1

=

x
n



∑

j
=
0

m
-
1





(

m

j
+
1

)



(

-

Assignees

• Imagination Tech Ltd

Inventors

• Rose Thomas
• Freiburghaus Max
• Mckemey Robert

Classifications

• G06F7/5525 Primary

  Roots or inverse roots of single operands · CPC title

• G06F2207/5521

  Inverse root of a number or a function, e.g. the reciprocal of a Pythagorean sum · CPC title

• G06F7/57

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• G06F7/575 Primary

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title

• G06F7/552

  Powers or roots {, e.g. Pythagorean sums} · CPC title