Apparatus and method for performing reciprocal estimation operation

Patent metadata

Field	Value
Publication number	US-9658827-B2
Application number	US-201414519787-A
Country	US
Kind code	B2
Filing date	Oct 21, 2014
Priority date	Oct 21, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A data processing apparatus has floating-point add circuitry for performing a floating-point add operation for adding or subtracting two floating-point operands. The apparatus also has reciprocal estimation circuitry for performing a reciprocal estimation operation on a first operand to generate a reciprocal estimate value which represents an estimate of a reciprocal of a first operand or an estimate or a reciprocal of the square root of the first operand. The reciprocal estimation circuitry is physically distinct from the floating-point adder circuitry, which allows both the reciprocal estimate and the add operations to be faster.

First claim

We claim:

1. A data processing apparatus comprising:
floating-point add circuitry to perform a floating-point addition operation for adding or subtracting two floating-point operands to generate a result floating-point operand; and
reciprocal estimation circuitry to perform a reciprocal estimation operation on a first operand to generate a reciprocal estimate value representing an estimate of a reciprocal of the first operand or an estimate of a reciprocal of the square root of the first operand;
wherein the reciprocal estimation circuitry is physically distinct from the floating-point add circuitry;
wherein the reciprocal estimation circuitry comprises exponent processing circuitry to generate an exponent of the reciprocal estimate value if the first operand is a floating-point operand; and
the exponent processing circuitry comprises:
a carry-save adder to add an inverted exponent value, a leading zero count value, and a bias adjustment value, to generate a sum value and carry value, wherein:
the inverted exponent value corresponds to an inverted version of the exponent of the first operand;
the leading zero count value is dependent on a number of leading zeroes in a significand of the first operand; and
the bias adjustment value is for biasing the exponent of the reciprocal estimate value according to a floating-point representation used for the reciprocal estimate value; and

a second adder to add the sum value and carry value generated by the carry-save adder to generate the exponent of the reciprocal estimate value.

2. The data processing apparatus according to claim 1 , wherein the floating-point add circuitry is capable of performing the floating-point addition operation in M processing cycles, and the reciprocal estimation circuitry is capable of performing the reciprocal estimation operation in N processing cycles, where N<M.

3. The data processing apparatus according to claim 1 , wherein the first operand is one of:
a fixed-point operand comprising a fixed-point significand; and
a floating-point operand comprising a floating-point significand and an exponent.

4. The data processing apparatus according to claim 1 , wherein the reciprocal estimation circuitry is capable of performing the reciprocal estimation operation on both fixed-point operands and floating-point operands.

5. The data processing apparatus according to claim 1 , wherein the reciprocal estimation circuitry is capable of performing the reciprocal estimation operation on both normal floating-point operands and subnormal floating-point operands.

6. The data processing apparatus according to claim 1 , wherein the reciprocal estimation circuitry comprises significand processing circuitry to generate a significand of the reciprocal estimate value.

7. The data processing apparatus according to claim 6 , wherein the significand processing circuitry comprises:
lookup operand generating circuitry to generate a lookup operand based on a significand of the first operand; and
a lookup table to map the lookup operand generated by the lookup operand generating circuitry to the significand of the reciprocal estimate value.

8. The data processing apparatus according to claim 7 , wherein the lookup operand generating circuitry comprises normalization circuitry to normalize the significand of the first operand if the first operand is a subnormal floating-point operand.

9. The data processing apparatus according to claim 1 , wherein the exponent processing circuitry comprises:
reciprocal exponent generation circuitry to generate the exponent of the reciprocal estimate value if the reciprocal estimate value represents the estimate of the reciprocal of the first operand; and
reciprocal square root exponent generation circuitry to generate the exponent of the reciprocal estimate value if the reciprocal estimate value represents the estimate of the reciprocal of the square root of the first operand.

10. The data processing apparatus according to claim 9 , wherein at least some circuitry is shared between the reciprocal exponent generation circuitry and the reciprocal square root exponent generation circuitry.

11. The data processing apparatus according to claim 1 , wherein if the reciprocal estimate value represents the estimate of the reciprocal of the first operand, then the exponent processing circuitry is configured to generate a biased exponent e′R of the reciprocal estimate value with a value equivalent to e′ R =e′ op +2*B−1+lzc+normal; where:
˜e′ op is an inverted version of a biased exponent e′ op of the first operand;
B is an exponent bias amount;
lzc represents a number of leading zeroes in a significand of the first operand if the first operand is subnormal; and
normal equals 1 if the first operand is normal and equals 0 if the first operand is subnormal.

12. The data processing apparatus according to claim 1 , wherein if the reciprocal estimate value represents the estimate of the reciprocal of the square root of the first operand, then the exponent processing circuitry is configured to generate a biased exponent e′R of the reciprocal estimate value with a value equivalent to:

e
R
′

=

B
+

B
-
1

2

-
1
+
normal
+

~

e
op
′

2

+

~

e
op
′

⁡

[
0
]

+

lzc
2

+

lzc
⁡

[
0
]

;

where:

~

e
op
′

2

is an inverted version of half a biased exponent e′ op of the first operand;
˜e′ op [0] is an inverted version of a least significant bit of the biased exponent e′ op of the first operand;
B is an exponent bias amount;
lzc represents a number of leading zeroes in a significand of the first operand if the first operand is subnormal;
lzc[0] is a least significant bit of lzc; and
normal equals 1 if the first operand is normal and equals 0 if the first operand is subnormal.

13. The data processing apparatus according to claim 1 , wherein one of the carry-save adder and the se

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lutz David Raymond
• Burgess Neil

Classifications

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F7/535

  Dividing only · CPC title

• G06F2207/48

  Indexing scheme relating to groups G06F7/48 - G06F7/575 · CPC title

• G06F7/5525

  Roots or inverse roots of single operands · CPC title

• G06F7/485 Primary

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title