Apparatus and method for performing floating-point square root operation

Patent metadata

Field	Value
Publication number	US-9710229-B2
Application number	US-201514728085-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Jul 24, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A data processing apparatus has a processing circuitry for performing a floating-point square root operation on a radicand value R to generate a result value. The processing circuitry has first square root processing circuitry for processing radicand values R which are not an exact power of two and second square root processing circuitry for processing radicand values which are an exact power of 2. Power-of-two detection circuitry detects whether the radicand value is an exact power of two and selects the output of the first or second square root processing circuitry as appropriate. This allows the result to be generated in fewer processing cycles when the radicand is a power of 2.

First claim

The invention claimed is:

1. A data processing apparatus comprising:
processing circuitry configured to perform a floating-point square root operation for determining a square root of a radicand value R having a radicand exponent and a radicand mantissa to generate a result value having a result exponent and a result mantissa;
wherein the processing circuitry comprises:
first square root processing circuitry configured to perform the floating-point square root operation for radicand values which are not an exact power of two;
second square root processing circuitry configured to perform the floating-point square root operation for radicand values which are an exact power of two, wherein the second square root processing circuitry is configured to generate the result value in fewer processing cycles than the first square root processing circuitry; and
power-of-two detection circuitry configured to detect whether the radicand value is an exact power of two, to control the processing circuitry to output the result value generated by the first square root processing circuitry if the radicand value is not an exact power of two, and to control the processing circuitry to output the result value generated by the second square root processing circuitry if the radicand value is an exact power of two.

2. The data processing apparatus according to claim 1 , wherein the power-of-two detection circuitry is configured to detect whether the radicand value is an exact power of two in parallel with the first square root processing circuitry starting to perform the floating-point square root operation on the radicand value.

3. The data processing apparatus according to claim 1 , wherein if the radicand value is a normal value, the power-of-two detection circuitry is configured to detect that the radicand value is an exact power of two if the radicand mantissa has a value of 1.0.

4. The data processing apparatus according to claim 1 , wherein if the radicand value is a subnormal value, the power-of-two detection circuitry is configured to detect that the radicand value is an exact power of two if the radicand mantissa includes only one bit having a value of 1.

5. The data processing apparatus according to claim 1 , wherein the floating-point square root operation comprises one of:
(i) a non-reciprocal floating-point square root operation for generating the result value equal to √{square root over (R)}; and
(ii) a reciprocal floating-point square root operation for generating the result value equal to

1
R

.

6. The data processing apparatus according to claim 1 , wherein the second square root processing circuitry is configured to generate the result value with:
the result mantissa having a predetermined mantissa value; and
the result exponent having a value corresponding to half an adjusted exponent.

7. The data processing apparatus according to claim 6 , wherein the predetermined mantissa value and the adjusted exponent are selected depending on whether the radicand value R is equal to two to the power of an even number or equal to two to the power of an odd number.

8. The data processing apparatus according to claim 7 , wherein if the radicand value R is equal to two to the power of an even number, then the predetermined mantissa has a value corresponding to 1.0.

9. The data processing apparatus according to claim 7 , wherein if the radicand value R is equal to two to the power of an odd number, then the predetermined mantissa has a value corresponding to the square root of two.

10. The data processing apparatus according to claim 7 , wherein if the floating-point square root operation is a non-reciprocal floating-point square root operation for generating the result value equal to √{square root over (R)}, and the radicand value R is equal to two to the power of an even number, then the adjusted exponent equals the radicand exponent.

11. The data processing apparatus according to claim 7 , wherein if the floating-point square root operation is a non-reciprocal floating-point square root operation for generating the result value equal to √{square root over (R)}, and the radicand value R is equal to two to the power of an odd number, then the adjusted exponent equals the radicand exponent minus one.

12. The data processing apparatus according to claim 7 , wherein if the floating-point square root operation is a reciprocal floating-point square root operation for generating the result value equal to

1
R

and the radicand value R is equal to two to the power of an even number, then the adjusted exponent equals −E, where E is the radicand exponent.

13. The data processing apparatus according to claim 7 , wherein if the floating-point square root operation is a reciprocal floating-point square root operation for generating the result value equal to

1
R

and the radicand value R is equal to two to the power of an odd number, then the adjusted exponent equals −E−1, where E is the radicand exponent.

14. The data processing apparatus according to claim 7 , wherein if the radicand value is a subnormal value which is an exact power of two, then the radicand mantissa has only one bit equal to 1 and a radicand exponent value equal to 0, and the second square root processing circuitry is configured to determine the radicand exponent E based on the position of said one bit equal to 1 within the radicand mantissa value.

15. The data processing apparatus according to claim 1 , wherein if the floating-point square root operation is a non-reciprocal floating-point square root operation for generating the result value equal to √{square root over (R)}, and the radicand value R is a normal value equal to two to the power of an even number, then the second square root processing circuitry is configured to generate the result value by:
generating the result mantissa with a value corresponding to 1.0;
inverting a most significant bit of a biased radicand exponent value to generate a first intermediate value, where the biased radicand exponent value equals the radicand exponent minus a bias value;
right shifting the first intermediate value by one bit position to generate a second intermediate value; and
inverting the most significant bit of the second intermediate value to generate a biased result exponent value equal to the result exponent minus the bias value.

16. The data processing apparatus according to claim 1 , wherein if the floating-point square root operation is a non-reciprocal floating-point square root operation for generating the result value equal to √{square root over (r)}, and the radicand value R is a normal value equal to two to the power of an odd number, then the second square root processing circuitry is configured to generate the result value by:
generating the result mantissa with a value corresponding to the square root of two;
inverting the most significant bit of a biased radicand exponent value to generate a first intermediate value, where the biased radicand exponent value equals the radicand exponent minus a bias value;
subtracting one from the first intermediate value to gener

Assignees

• Advanced Risc Mach Ltd

Inventors

• Burgess Neil
• Lutz David Raymond

Classifications

• G06F7/5525 Primary

  Roots or inverse roots of single operands · CPC title

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title