Multiplier unit with speculative rounding for use with division and square-root operations

Patent metadata

Field	Value
Publication number	US-9645791-B2
Application number	US-201414305651-A
Country	US
Kind code	B2
Filing date	Jun 16, 2014
Priority date	Jun 16, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

Embodiments of a multiplier unit that may be used for division and square root operations are disclosed. The embodiments may provide a reduced and fixed latency for denormalization and rounding used in the division and square root operations. A storage circuit may be configured to receive first and second source operands. A multiplier circuit may be configured to perform a plurality of multiplication operations dependent upon the first and second source operands. Each result after an initial result of the multiplier may also depend on at least one previous result. Circuitry may be configured to perform a shift operation and a rounding operation on a given result of the plurality of results. An error of the given result may be less than a predetermined threshold value.

First claim

What is claimed is:

1. An apparatus, comprising:
a storage circuit configured to receive and store a first source operand and a second source operand;
a multiplier circuit configured to perform, responsive to an operation, a plurality of multiplication operations dependent upon the first source operand and the second source operand to generate a respective plurality of results, wherein each result after an initial result is dependent upon at least one previous result; and
circuitry configured to:
perform a shift operation on a given result of the plurality of results to generate a shifted result, wherein an error of the given result of the plurality of results is less than a predetermined threshold value; and
perform a rounding operation on the shifted result.

2. The apparatus of claim 1 , wherein each result of the plurality of results corresponds to an approximation of a result of the operation performed by the multiplier circuit, wherein the operation includes a division operation or a square root operation.

3. The apparatus of claim 1 , wherein to perform the shift operation, the circuitry is further configured to perform the shift operation responsive to a determination that the given result is denormal or an integer.

4. The apparatus of claim 1 , wherein to perform the rounding operation, the circuitry is further configured to perform a first rounding operation and a second rounding operation.

5. The apparatus of claim 1 , wherein each result of the plurality of results corresponds to an approximation of a square root of the first source operand.

6. The apparatus of claim 5 , wherein to perform the shift operation, the circuitry is further configured to determine a number of bits to shift dependent upon the first source operand and the second source operand.

7. The apparatus of claim 4 , wherein the first rounding operation comprises a decrement operation, and the second rounding operation comprises an increment operation.

8. A method, comprising:
receiving a first operand and a second operand;
performing an operation dependent upon the first operand and the second operand, wherein the operation includes a plurality of iterations;
performing, in response to a determination that the operation has completed, a shift operation on an approximation of a result of the operation to generated a shifted approximation; and
performing a rounding operation dependent upon the shifted approximation.

9. The method of claim 8 , wherein the operation comprises a division operation.

10. The method of claim 8 , wherein the operation comprises a square root operation.

11. The method of claim 8 , wherein performing the operation comprises performing a back multiplication operation.

12. The method of claim 11 , wherein performing the rounding operation comprises performing a first rounding operation dependent upon the shifted approximation and a second rounding operation dependent upon the shifted approximation.

13. The method of claim 12 , further comprising selecting a result from the first rounding operation and the second rounding operation dependent upon a result of the back multiplication operation.

14. The method of claim 12 , wherein the first rounding operation comprises a decrement operation, and the second rounding operation comprises an increment operation.

15. A system, comprising:
a register configured to:
receive at least two N-bit operands, wherein N is a positive integer; and
store the at least two N-bit operands;

a multiplier circuit configured to:
multiply a first M-bits of a first operand of the at least two N-bit operands by a first M-bits of a second operand of the at least two N-bit operands to generate a first product, wherein M is a positive integer less than N;
multiply the first M-bits of the first operand of the at least two N-bit operands by a last N-M bits of the second operand to generate a second product;
multiply a last N-M bits of the first operand of the at least two N-bit operands by the first M-bits of the second operand of the at least two N-bit operands to generate a third product; and
add the first product, the second product, and the third product, to generate a result.

16. The system of claim 15 , wherein the system further comprises circuitry configured to:
perform a shift operation on the result; and
perform a rounding operation on the result.

17. The system of claim 16 , wherein to perform the rounding operation, the circuitry is further configured to perform, in parallel, a decrement operation on the result to generate a first rounded result, and an increment operation on the result to generate a second rounded result.

18. The system of claim 17 , wherein the circuitry is further configured to perform a back multiplication dependent upon the result, and wherein to perform the rounding operation, the circuitry is further configured to select one of the first rounded result and the second rounded result dependent upon a result of the back multiplication.

19. The system of claim 16 , wherein to perform the shift operation, the circuitry is further configured to determine a number of bits to shift dependent upon the at least two N-bit operands.

20. The system of claim 16 , wherein to perform the shift operation, the circuitry is further configured to perform the shift operation responsive to a determination that the result is denormal or an integer.

Assignees

• Apple Inc

Inventors

• Alvarez-Heredia Boris S
• Catovic Edvin

Classifications

• G06F2207/5355

  Using iterative approximation not using digit recurrence, e.g. Newton Raphson or Goldschmidt · CPC title

• G06F7/5525

  Roots or inverse roots of single operands · CPC title

• G06F7/49947

  Rounding · CPC title

• G06F7/535 Primary

  Dividing only · CPC title

• G06F7/49936

  Normalisation mentioned as feature only · CPC title