Execution unit for calculations with masked data
US-2019379529-A1 · Dec 12, 2019 · US
Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F7/575 |
| Official title | Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry |
| Display label | Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry |
| Total patents | 384 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 1 |
| 2016 | 7 |
| 2017 | 8 |
| 2018 | 22 |
| 2019 | 25 |
| 2020 | 31 |
| 2021 | 56 |
| 2022 | 64 |
| 2023 | 51 |
| 2024 | 61 |
| 2025 | 47 |
| 2026 | 11 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Data processing system and data processing method
US-2019369963-A1 · Dec 5, 2019 · US
Adder-subtractor circuit and method of controlling adder-subtractor circuit
US-2019339940-A1 · Nov 7, 2019 · US
Generalized acceleration of matrix multiply accumulate operations
US-2019324747-A1 · Oct 24, 2019 · US
Processor and Arithmetic Processing Device Having the Same
US-2019286420-A1 · Sep 19, 2019 · US
Trailing or Leading Digit Anticipator
US-2019286422-A1 · Sep 19, 2019 · US
Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features
US-10387319-B2 · Aug 20, 2019 · US
Computational processor-in-memory with enhanced strided memory access
US-2019235780-A1 · Aug 1, 2019 · US
Trailing or leading digit anticipator
US-10346137-B2 · Jul 9, 2019 · US
Generalized acceleration of matrix multiply accumulate operations
US-10338919-B2 · Jul 2, 2019 · US
Floating point to fixed point conversion
US-2019199370-A1 · Jun 27, 2019 · US
Memory load and arithmetic load unit (ALU) fusing
US-10275217-B2 · Apr 30, 2019 · US
Semiconductor device and memory access method
US-2019095324-A1 · Mar 28, 2019 · US
Floating point to fixed point conversion
US-10224954-B1 · Mar 5, 2019 · US
Continuous Carry-Chain Packing
US-2019042200-A1 · Feb 7, 2019 · US
Floating-Point Dynamic Range Expansion
US-2019042193-A1 · Feb 7, 2019 · US
Trailing or Leading Digit Anticipator
US-2019034171-A1 · Jan 31, 2019 · US
Computational array microprocessor system using non-consecutive data formatting
US-2019026249-A1 · Jan 24, 2019 · US
Vector computational unit
US-2019026250-A1 · Jan 24, 2019 · US
Accelerated mathematical engine
US-2019026078-A1 · Jan 24, 2019 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F7/575?
- CPC G06F7/575 is the Cooperative Patent Classification code for “Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry.”
- How many patents are filed under CPC G06F7/575 (Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry)?
- Our database includes 384 publications tagged with this CPC code.
- Is patent activity under CPC G06F7/575 growing?
- Publication counts under this code: 61 in 2024 vs 47 in 2025 (latest complete years).