Heterogeneous metal line compositions for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-2020044049-A1
Application number	US-201916537020-A
Country	US
Kind code	A1
Filing date	Aug 9, 2019
Priority date	Nov 30, 2017
Publication date	Feb 6, 2020
Grant date	—

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

First claim

1 . (canceled)

2 . An integrated circuit structure, comprising:
a first plurality of conductive interconnect lines in and spaced apart by a first inter-layer dielectric (ILD) layer above a substrate, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material; and a second plurality of conductive interconnect lines in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the first conductive barrier material is different in composition from the second conductive barrier material, and wherein individual ones of the first plurality of conductive interconnect lines are along a first direction, and individual ones of the second plurality of conductive interconnect lines are along a second direction orthogonal to the first direction.

3 . The integrated circuit structure of claim 2 , wherein the first conductive barrier material comprises an outer layer distal from the first conductive fill material and an inner layer proximate to the first conductive fill material, the outer layer comprising titanium and nitrogen, and the inner layer comprising tungsten, nitrogen and carbon.

4 . The integrated circuit structure of claim 3 , wherein the outer layer has a thickness of approximately 2 nanometers, and the inner layer has a thickness of approximately 0.5 nanometers.

5 . The integrated circuit structure of claim 2 , wherein the second conductive barrier material comprises an outer layer distal from the second conductive fill material and an inner layer proximate to the second conductive fill material, the outer layer comprising tantalum, and the inner layer comprising ruthenium.

6 . The integrated circuit structure of claim 5 , wherein the outer layer further comprises nitrogen.

7 . The integrated circuit structure of claim 2 , wherein individual ones of the second plurality of conductive interconnect lines comprise a conductive cap layer on a top of the second conductive fill material.

8 . The integrated circuit structure of claim 7 , wherein the conductive cap layer is not on a top of the second conductive barrier material.

9 . The integrated circuit structure of claim 2 , further comprising:
a conductive via on and electrically coupled to an individual one of the first plurality of conductive interconnect lines, wherein an individual one of the second plurality of conductive interconnect lines is on and electrically coupled to the conductive via.

10 . The integrated circuit structure of claim 9 , wherein the conductive via comprises the second conductive barrier material along sidewalls and a bottom of the second conductive fill material.

11 . The integrated circuit structure of claim 9 , wherein the second ILD layer is on an etch-stop layer on the first ILD layer, and wherein the conductive via is in the second ILD layer and in an opening of the etch-stop layer.

12 . The integrated circuit structure of claim 11 , wherein the first and second ILD layers comprise silicon, carbon and oxygen, and wherein the etch-stop layer comprises silicon and nitrogen.

13 . The integrated circuit structure of claim 2 , wherein individual ones of the first plurality of conductive interconnect lines have a first width, and individual ones of the second plurality of conductive interconnect lines have a second width greater than the first width.

14 . An integrated circuit structure, comprising:
a first plurality of conductive interconnect lines in and spaced apart by a first inter-layer dielectric (ILD) layer above a substrate, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material, and wherein individual ones of the first plurality of conductive interconnect lines are along a first direction; a second plurality of conductive interconnect lines in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise the first conductive barrier material along sidewalls and a bottom of the first conductive fill material, and wherein individual ones of the second plurality of conductive interconnect lines are along a second direction orthogonal to the first direction; a third plurality of conductive interconnect lines in and spaced apart by a third ILD layer above the second ILD layer, wherein individual ones of the third plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the first conductive barrier material is different in composition from the second conductive barrier material, and wherein individual ones of the first plurality of conductive interconnect lines are along the first direction; a fourth plurality of conductive interconnect lines in and spaced apart by a fourth ILD layer above the third ILD layer, wherein individual ones of the fourth plurality of conductive interconnect lines comprise the second conductive barrier material along sidewalls and a bottom of the second conductive fill material, and wherein individual ones of the fourth plurality of conductive interconnect lines are along the second direction; a fifth plurality of conductive interconnect lines in and spaced apart by a fifth ILD layer above the fourth ILD layer, wherein individual ones of the fifth plurality of conductive interconnect lines comprise the second conductive barrier material along sidewalls and a bottom of the second conductive fill material, and wherein individual ones of the fifth plurality of conductive interconnect lines are along the first direction; and a sixth plurality of conductive interconnect lines in and spaced apart by a sixth ILD layer above the fifth ILD layer, wherein individual ones of the sixth plurality of conductive interconnect lines comprise the second conductive barrier material along sidewalls and a bottom of the second conductive fill material, and wherein individual ones of the sixth plurality of conductive interconnect lines are along the second direction.

15 . The integrated circuit structure of claim 14 , wherein the second conductive fill material consists essentially of copper, and wherein the first conductive fill material consists essentially of cobalt.

16 . The integrated circuit structure of claim 14 , wherein the first conductive fill material comprises copper having a first concentration of a dopant impurity atom, and wherein the second conductive fill material comprises copper having a second concentration of the dopant impurity atom, the second concentration of the dopant impurity atom less than the first concentration of the dopant impurity atom.

17 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a first plurality of conductive interconnect lines in and spaced apart by a first inter-layer dielectric (ILD) layer above a substrate, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material; and
a second plurality of conductive interconnect lines in and spaced apart by a seco

Assignees

• Intel Corp

Inventors

• Yeoh Andrew W
• Steigerwald Joseph
• Shin Jinhong
• Chikarmane Vinay
• Auth Christopher P

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title