Multi-chip package and method of providing die-to-die interconnects in same

Patent metadata

Field	Value
Publication number	US-2018145031-A1
Application number	US-201815876080-A
Country	US
Kind code	A1
Filing date	Jan 19, 2018
Priority date	Jun 24, 2009
Publication date	May 24, 2018
Grant date	—

Abstract

A multi-chip package includes a substrate ( 110 ) having a first side ( 111 ), an opposing second side ( 112 ), and a third side ( 213 ) that extends from the first side to the second side, a first die ( 120 ) attached to the first side of the substrate and a second die ( 130 ) attached to the first side of the substrate, and a bridge ( 140 ) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity ( 615, 915 ) in the substrate or between the substrate and a die layer ( 750 ). The bridge may constitute an active die and may be attached to the substrate using wirebonds ( 241, 841, 1141, 1541 ).

First claim

What is claimed is:

1 . A multi-chip package comprising:
a substrate having a first side, an opposing second side, and a third side that extends from the first side to the second side, the third side constituting a portion of an outside perimeter of the substrate; a first die attached to the first side of the substrate and a second die attached to the first side of the substrate; and a bridge adjacent to the third side of the substrate and attached to the first die and to the second die, wherein no portion of the substrate is underneath the bridge and wherein the bridge creates a connection between the first die and the second die.

2 . A method of providing die-to-die interconnects in a multi-chip package, the method comprising:
providing a substrate having a first side, an opposing second side, and a third side that extends from the first side to the second side; attaching a first die to the first side of the substrate such that a portion of the first die extends beyond an edge of the first side of the substrate; attaching a second die to the first side of the substrate such that a portion of the second die extends beyond the edge of the first side of the substrate; providing a bridge containing a plurality of electrically or optically conductive features; positioning the bridge adjacent to the third side of the substrate such that no portion of the substrate is underneath the bridge; and attaching the bridge to the first die and to the second die, thereby creating a connection between the first die and the second die.

3 . The method of claim 2 wherein:
the bridge comprises silicon.

4 . The method of claim 3 wherein:
the bridge comprises an active die that constitutes a third die of the multi-chip package; and
the bridge is attached to the first die and to the second die using flip-chip connections.

5 . The method of claim 4 further comprising:
attaching the bridge to the substrate using a wirebond.

6 . The method of claim 3 wherein:
attaching the bridge comprises using a thermocompression bonding process.

7 . The method of claim 3 wherein:
attaching the bridge comprises using a solder reflow process.

8 . The method of claim 3 wherein:
providing the substrate comprises forming an aperture through the substrate such that the third side constitutes a portion of an inside perimeter of the substrate.

9 . The method of claim 3 wherein:
providing the substrate comprises forming a slot in the substrate such that the third side constitutes a portion of an outside perimeter of the substrate.

10 . A method of providing die-to-die interconnects in a multi-chip package, the method comprising:
attaching a first die and a second die to a carrier; attaching a bridge to the first die and to the second die; providing a substrate; and attaching the first die and the second die to the substrate.

11 . The method of claim 10 wherein:
the substrate has a cavity therein; and
attaching the first die and the second die to the substrate comprises locating the bridge within the cavity.

12 . The method of claim 10 further comprising:
removing the carrier.

13 . The method of claim 10 wherein:
the carrier comprises a heat spreader.

14 . The method of claim 10 wherein:
attaching the bridge comprises using a thermocompression bonding process.

15 . The method of claim 10 wherein:
the bridge comprises silicon.

16 . The method of claim 15 wherein:
the bridge comprises an active die that constitutes a third die of the multi-chip package;
the bridge is attached to the first die and to the second die using flip-chip connections; and
the method further comprises attaching the bridge to the substrate using a wirebond.

17 . A multi-chip package comprising:
a substrate containing a cavity having a plurality of pads therein; a first die attached to the substrate and a second die attached to the substrate; a bridge having a first side and an opposing second side; and a plurality of joints at the second side of the bridge, wherein: the first die and the second die are attached to the first side of the bridge; at least a portion of the bridge is located within the cavity such that the plurality of joints are aligned with the plurality of pads; and the bridge creates a connection between the first die and the second die.

18 . The multi-chip package of claim 17 wherein:
the bridge comprises silicon.

19 . The multi-chip package of claim 18 wherein:
the bridge is attached to the first die and to the second die using flip-chip connections;
the bridge comprises an active die that constitutes a third die of the multi-chip package; and
the bridge is attached to the substrate using a wirebond.

20 . The multi-chip package of claim 18 wherein:
the first die has a first portion containing a first plurality of interconnect structures and a second portion containing a second plurality of interconnect structures;
the second die has a third portion containing a third plurality of interconnect structures and a fourth portion containing a fourth plurality of interconnect structures;
the first plurality of interconnect structures and the third plurality of interconnect structures have a first pitch;
the second plurality of interconnect structures and the fourth plurality of interconnect structures have a second pitch that is different from the first pitch; and
the first portion and the third portion are attached to the bridge.

21 . A method of providing die-to-die interconnects in a multi-chip package, the method comprising:
providing a substrate having a plurality of embedded pads; forming a cavity in the substrate such that the pads are exposed at a floor of the cavity; providing a bridge having bumps thereon corresponding to the pads; placing the bridge in the cavity and aligning the bumps and the pads to each other; providing a first die and a second die; and attaching the first die and the second die to the bridge and the substrate.

22 . The method of claim 21 wherein:
the bridge comprises silicon.

23 . The method of claim 22 wherein:
the bridge comprises an active die that constitutes a third die of the multi-chip package;
the bridge is attached to the first die and to the second die using flip-chip connections; and
the method further comprises attaching the bridge to the substrate using a wirebond.

24 . The method of claim 22 wherein:
forming the cavity comprises using one of a laser milling and a plasma etching process.

25 . A multi-chip package comprising:
a substrate; a first active die attached to the substrate using a first flip-chip connection; and a second active die, wherein the second active die is attached to the first active die using a second flip-chip connection and wherein the second active die is also attached to the substrate using a wirebond, wherein: the second active die has a first region and a second region; the first region is an overlap region located between the substrate and a portion of the first active die; and the second flip-chip connection is located in the first region of the second active die and the wirebond is attached to the second active die in the second region.

26 . The multi-chip package of claim 25 wherein:
the first region of the second active die has a first section and a second section; and
the first section cont

Assignees

• Intel Corp

Inventors

• Braunisch Henning
• Chiu Chia-Pin
• Aleksov Aleksandar
• Au Hinmeng
• Lotz Stefanie M
• Swan Johanna M
• Sharan Sujit

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title