Vco-based continuous-time sigma delta modulator equipped with truncation circuit and phase-domain excess loop delay compensation

Patent metadata

Field	Value
Publication number	US-2017194984-A1
Application number	US-201715461502-A
Country	US
Kind code	A1
Filing date	Mar 17, 2017
Priority date	Jun 10, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.

First claim

What is claimed is:

1 . A continuous-time sigma-delta modulator, comprising:
a VCO-based quantizer, arranged to generate a thermometer code based on an input signal and a feedback signal; a rotator, coupled to the VCO-based quantizer, arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern; a truncation circuit, coupled to the rotator, arranged to extract a most significant bit (MSB) part from the rearranged thermometer code; and a digital-to-analog converter (DAC), coupled to the truncation circuit, arranged to generate the feedback signal according to at least the MSB part.

2 . The continuous-time sigma-delta modulator of claim 1 , wherein bits with a specific bit interval of the rearranged thermometer code are determined to be the MSB part.

3 . The continuous-time sigma-delta modulator of claim 2 , wherein remaining bits of the rearranged thermometer are determined to be a least significant bit (LSB) set, and the truncation circuit comprises:
a transition detector, arranged to determine a 0 and 1 bit transition position of the MSB part and generate a transition position; and a multiplexer, arranged to determine a LSB part from the LSB set according to the transition position.

4 . The continuous-time sigma-delta modulator of claim 2 , wherein the specific bit interval of the rearranged thermometer code is determined based on a truncation bit number.

5 . The continuous-time sigma-delta modulator of claim 1 , wherein the specific pattern includes at most a single 0 and 1 bit transition.

6 . The continuous-time sigma-delta modulator of claim 1 , further comprising:
an excess loop delay compensation (ELDC) circuit, coupled between the rotator and the truncation circuit, wherein the ELDC circuit is arranged to generate the phase shift to the rotator based on the MSB part.

7 . The continuous-time sigma-delta modulator of claim 1 , wherein the truncation circuit is further arranged to extract a least significant bit (LSB) part from the rearranged thermometer code, and the continuous-time sigma-delta modulator further comprises:
a shaping circuit, coupled between the rotator and the truncation circuit, wherein the shaping circuit is arranged to generate the phase shift to the rotator based on the LSB part.

8 . The continuous-time sigma-delta modulator of claim 7 , wherein the LSB part is frequency-shaped to high frequency.

9 . The continuous-time sigma-delta modulator of claim 1 , wherein the truncation circuit is further arranged to extract a least significant bit (LSB) part from the rearranged thermometer code, and the continuous-time sigma-delta modulator further comprises:
a shaping circuit, coupled between the VCO-based quantizer and the truncation circuit, wherein the shaping circuit is arranged to generate the phase shift based on the LSB part.

10 . The continuous-time sigma-delta modulator of claim 9 , wherein the LSB part is frequency-shaped to high frequency.

11 . The continuous-time sigma-delta modulator of claim 1 , wherein the truncation circuit is further arranged to extract a least significant bit (LSB) part from the rearranged thermometer code, and the DAC is arranged to generate the feedback signal according to the MSB part and the LSB part.

12 . The continuous-time sigma-delta modulator of claim 1 , wherein the rotator comprises:
an XOR circuit, arranged to generate the phase-shifted thermometer code by performing an XOR operation on the thermometer code and the phase shift; and a switch circuit, arranged to generate the rearranged thermometer code based on the phase-shifted thermometer code to comply with the specific pattern.

13 . A continuous-time sigma-delta modulator, comprising:
a VCO-based quantizer, arranged to generate a thermometer code based on an input signal and a feedback signal; an XOR circuit, arranged to generate a phase-shifted thermometer code by performing an XOR operation on the thermometer code and a phase shift; a truncation circuit, coupled to the XOR circuit, arranged to extract a most significant bit (MSB) part from the phase-shifted thermometer code; and a digital-to-analog converter (DAC), coupled to the truncation circuit, arranged to generate the feedback signal according to at least the MSB part.

14 . The continuous-time sigma-delta modulator of claim 13 , wherein the truncation circuit is arranged to generate the MSB part according to a sum of bits with a specific bit interval of the phase-shifted thermometer code and a truncation bit number.

15 . The continuous-time sigma-delta modulator of claim 14 , wherein remaining bits of the rearranged thermometer are determined to be a least significant bit (LSB) set, and the truncation circuit comprises:
a bit extension circuit, arranged to extend the phase-shifted thermometer code by inserting a bit duplicated from a least significant bit of the phase-shifted thermometer code to a bit position higher than a most significant bit of the phase-shifted thermometer code; a transition detector, arranged to determine a 0 to 1 bit transition position and a 1 to 0 bit transition position of the bits with the specific bit interval of the bit extended phase-shifted thermometer code and generate a first transition position and a second transition position; a multiplexer, arranged to determine a first LSB result and a second LSB result from the LSB set according to the first transition position and the second transition position; and a LSB generator, arranged to generate a LSB part according to the first LSB result and the second LSB result.

16 . The continuous-time sigma-delta modulator of claim 14 , wherein the specific bit interval of the rearranged thermometer code is determined based on the truncation bit number.

17 . The continuous-time sigma-delta modulator of claim 13 , wherein the truncation circuit is arranged to generate the MSB part according to a sum of bits with a specific bit interval of the phase-shifted thermometer code.

18 . The continuous-time sigma-delta modulator of claim 17 , wherein remaining bits of the rearranged thermometer are determined to be a least significant bit (LSB) set, and the truncation circuit comprises:
a transition detector, arranged to determine a 0 to 1 bit transition position and a 1 to 0 bit transition position of the bits with the specific bit interval of the bit extended phase-shifted thermometer code and generate a first transition position and a second transition position; a multiplexer, arranged to determine a first LSB result and a second LSB result from the LSB set according to the first transition position and the second transition position; and a LSB generator, arranged to generate a LSB part according to the first LSB result and the second LSB result.

19 . The continuous-time sigma-delta modulator of claim 18 , wherein a number of bit transition positions detected by the transition detector is equal to or greater than two.

20 . The continuous-time sigma-delta modulator of claim 18 , wherein multiple LSB parts are detected with aid of the transition detector, and are sent to the DAC or the XOR circuit after applying processing of a rotating splitting truncation circuit (RSTC) within the continuous-time sigma-delta modulator.

21 . The continuous-time sigma-delta modulator of claim 20 , wherein during the processing of the RSTC, a predetermin

Assignees

• Mediatek Inc

Inventors

• Huang Sheng-Jui
• Ashburn Jr Michael A
• Kesharwani Divya
• Egan Nathan

Classifications

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M3/37 Primary

  Compensation or reduction of delay or phase error · CPC title

• H03M3/428

  with lower resolution, e.g. single bit, feedback · CPC title

• H03M1/86

  with intermediate conversion to frequency of pulses · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title