Signal modulation circuit

Patent metadata

Field	Value
Publication number	US-2016241256-A1
Application number	US-201615137129-A
Country	US
Kind code	A1
Filing date	Apr 25, 2016
Priority date	Jun 11, 2013
Publication date	Aug 18, 2016
Grant date	—

Abstract

Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.

First claim

What is claimed is:

1 . A signal modulation circuit for performing delta sigma modulation on an input signal in synchronization with a clock signal to output the modulated signal, the circuit comprising:
a subtractor for calculating a difference between the input signal and a feedback signal; an integrator for integrating an output signal from the subtractor; a zero level inserting circuit for inserting a zero level into the signal integrated by the integrator at timing synchronized with the clock signal; a quantizer for delaying the signal output from the zero level inserting circuit and quantizing the delayed signal; and a feedback circuit for feeding back the signal quantized by the quantizer to the input signal.

2 . The signal modulation circuit according to claim 1 , wherein
the zero level inserting circuit includes a frequency divider for dividing a frequency of the clock signal, and a chopper circuit that operates according to the clock signal whose frequency is divided by the frequency divider.

3 . The signal modulation circuit according to claim 1 , wherein
the quantizer is configured by a D-type flip-flop.

4 . The signal modulation circuit according to claim 1 , wherein
the zero level inserting circuit and the quantizer are configured by a D-type flip-flop, and the clock signal is supplied to a reset terminal of the D-type flip-flop.

5 .- 11 . (canceled)

Assignees

• Onkyo Kk

Inventors

• Nakanishi Yoshinori
• Kawaguchi Tsuyoshi
• Sekiya Mamoru

Classifications

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• G11B20/10009

  Improvement or modification of read or write signals · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• H03M3/37 Primary

  Compensation or reduction of delay or phase error · CPC title

• H03M3/346

  by suppressing active signals at predetermined times, e.g. muting, using non-overlapping clock phases · CPC title