SAR ADC and method thereof

Patent metadata

Field	Value
Publication number	US-9385740-B2
Application number	US-201514919830-A
Country	US
Kind code	B2
Filing date	Oct 22, 2015
Priority date	Nov 7, 2014
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.

First claim

What is claimed is:

1. A successive approximation register analog to digital converter, for generating a digital code in response to a differential analog input signal, comprising:
a comparator, having a first input terminal and a second input terminal;
an input switch unit, arranged to couple the differential analog input signal to the comparator during a sampling phase and decouple the differential analog input signal to the comparator during a conversion phase;
a positive conversion capacitor array, comprising a plurality of first positive capacitors and a plurality of first positive switches, arranged to sample a positive end of the differential analog input signal during the sampling phase, wherein each first positive capacitor is coupled between the first input terminal of the comparator and a corresponding first positive switch, respectively, for selectively coupling the first positive capacitor to either a first reference voltage or a common voltage;
a negative conversion capacitor array, comprising a plurality of first negative capacitors and a plurality of first negative switches, arranged to sample a negative end of the differential analog input signal during the sampling phase, wherein each first negative capacitor is coupled between the second input terminal of the comparator and a corresponding first negative switch, respectively, for selectively coupling the first negative capacitor to either the first reference voltage or the common voltage; and
a successive approximation register (SAR) controller, arranged to reset the first positive switches and the first negative switches at the end of the sampling phase to change an input voltage difference between the first and second input terminals of the comparator into a residual signal, generate an intermediate digital code to control the first positive switches and the first negative switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generate the digital code according to the intermediate digital code, and use an inverted intermediate digital code to control the first positive switches and the first negative switches at the end of the conversion phase.

2. The converter of claim 1 , further comprises:
a positive scaling capacitor array, comprising a plurality of second positive capacitors and a plurality of second positive switches, arranged to sample the positive end of the differential analog input signal during the sampling phase, wherein each second positive capacitor is coupled between the first input terminal of the comparator and a corresponding second positive switch, respectively, for selectively coupling the second positive capacitor to either a second reference voltage or the common voltage;
a negative scaling capacitor array, comprising a plurality of second negative capacitors and a plurality of second negative switches, arranged to sample the negative end of the differential analog input signal during the sampling phase, wherein each second negative capacitor is coupled between the second input terminal of the comparator and a corresponding second negative switch, respectively, for selectively coupling the second negative capacitor to either the second reference voltage or the common voltage,
wherein the SAR controller resets the second positive switches and the second negative switches at the end of the sampling phase.

3. The converter of claim 2 , wherein the SAR controller uses an inverted intermediate digital code to control the second positive switches and the second negative switches at the end of the conversion phase.

4. The converter of claim 2 , wherein the SAR controller uses the intermediate digital code to control the second positive switches and the second negative switches at the end of the conversion phase.

5. The converter of claim 2 , wherein a second capacitance value of each second positive and negative capacitor is K times of a first capacitance value of the corresponding first positive and negative capacitor, K being a positive real number.

6. The converter of claim 2 , wherein the second reference voltage is K times of the first reference voltage, K being a positive real number.

7. A successive approximation register analog to digital converter, for generating a digital code in response to a differential analog input signal, comprising:
a comparator, having a first input terminal and a second input terminal;
an input switch with polarity inversion unit, arranged to couple the differential analog input signal to the comparator during a sampling phase and decouple the differential analog input signal to the comparator during a conversion phase, couple a positive and negative end of the differential analog input signal to the first and second input terminal of the comparator, respectively, in a normal cycle, and couple the positive and negative end of the differential analog input signal to the second and first input terminal of the comparator, respectively, in an alternate cycle, wherein each of the normal cycle and the alternate cycle comprises the sampling phase and the conversion phase;
a positive conversion capacitor array, comprising a plurality of first positive capacitors and a plurality of first positive switches, arranged to sample voltage at the first input terminal of the comparator during the sampling phase, wherein each first positive capacitor is coupled between the first input terminal of the comparator and a corresponding first positive switch, respectively, for selectively coupling the first positive capacitor to either a first reference voltage or a common voltage;
a negative conversion capacitor array, comprising a plurality of first negative capacitors and a plurality of first negative switches, arranged to sample voltage at the second input terminal of the comparator during the sampling phase, wherein each first negative capacitor is coupled between the second input terminal of the comparator and a corresponding first negative switch, respectively, for selectively coupling the first negative capacitor to either the first reference voltage or the common voltage; and
a successive approximation register (SAR) controller, arranged to reset the first positive switches and the first negative switches at the end of the sampling phase to change an input voltage difference between the first and second input terminals of the comparator into a residual signal, generate an intermediate digital code to control the first positive switches and the first negative switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, and generate the digital code by inverting the intermediate digital code in every alternate cycle.

8. The converter of claim 7 , further comprises:
a positive scaling capacitor array, comprising a plurality of second positive capacitors and a plurality of second positive switches, arranged to sample voltage at the first input terminal of the comparator during the sampling phase, wherein each second positive capacitor is coupled between the first input terminal of the comparator and a corresponding second positive switch, respectively, for selectively coupling the second positive capacitor to either a second reference voltage or the common voltage;
a negative scaling capacitor array, comprising a plurality of second negative capacitors and a plurality of second negative switches, arranged to sample voltage at the second input terminal of the comparator during the sampling phase, wherein each second negative capacitor is coupled between the second input terminal of the comparator and a corresponding second negative switch, respectively, for selectively coupling the second neg

Assignees

• Mediatek Inc

Inventors

• Wang Chi Yun
• Tsai Jen-Che
• Chu Shu-Wei

Classifications

• H03M1/403

  using switched capacitors · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/0854

  of quantisation noise · CPC title