Excess loop delay compensation (ELC) for an analog to digital converter (ADC)

Patent metadata

Field	Value
Publication number	US-9325341-B2
Application number	US-201414475852-A
Country	US
Kind code	B2
Filing date	Sep 3, 2014
Priority date	Sep 3, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.

First claim

What is claimed is:

1. A circuit comprising:
a quantizer configured to convert an analog input signal to a digital signal, the quantizer comprising:
a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer, wherein the first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction; and
a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction, wherein the plurality of excess loop delay (ELD) compensation paths compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer, and wherein a set of second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.

2. The circuit of claim 1 , wherein the plurality of ELD compensation paths are programmable to compensate for different excess loop delays.

3. The circuit of claim 2 , wherein the plurality of ELD compensation paths are associated with coefficients that are programmable to different values.

4. The circuit of claim 1 , wherein an ELD compensation path in the plurality of ELD compensation paths has a different resolution then the digital signal.

5. The circuit of claim 1 , wherein the plurality of ELD compensation paths are coupled to a capacitor array of the first DAC.

6. The circuit of claim 4 , wherein the plurality of ELD compensation paths comprise a plurality of capacitor arrays coupled to the capacitor array of the first DAC.

7. The circuit of claim 1 , wherein:
the quantizer includes a comparator configured to compare the analog input signal to a reference and output a digital value for the digital signal, and
the summing junction is coupled to the comparator.

8. The circuit of claim 7 , wherein the quantizer includes a successive approximation register (SAR) configured to store the digital value from the comparator.

9. The circuit of claim 7 , wherein the analog input signal is stored in a sample and hold circuit, and then input into the summing junction.

10. The circuit of claim 1 , wherein the summing junction combines the analog input signal combined with the second corresponding analog value from the second feedback path, the first corresponding analog value from the first feedback path, and a plurality of values from the plurality of compensation paths.

11. The circuit of claim 1 , wherein each ELD compensation path in the plurality of ELD compensation paths comprises a set of delay elements to provide a different delay.

12. A system comprising:
a loop filter configured to receive an analog input signal;
a quantizer configured to convert the analog input signal to a digital signal, the quantizer comprising a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer, wherein the first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction; and
a second feedback path coupled from the output of the quantizer to input of the loop filter, wherein a set of second DACs in the second feedback path converts the digital signal to a second corresponding analog value for combining with the analog input signal in the loop filter,
wherein the quantizer comprises a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction, and wherein the plurality of excess loop delay (ELD) compensation paths compensate for excess loop delay from the second feedback path.

13. The system of claim 12 , wherein the plurality of ELD compensation paths are programmable to compensate for different excess loop delays.

14. The system of claim 13 , wherein the plurality of ELD compensation paths are associated with coefficients that are programmable to different values.

15. The system of claim 12 , wherein an ELD compensation path in the plurality of ELD compensation paths has a different resolution then the digital signal.

16. The system of claim 12 , wherein the plurality of ELD compensation paths are coupled to a capacitor array of the first DAC.

17. The system of claim 15 , wherein the plurality of ELD compensation paths comprise a plurality of capacitor arrays coupled to the capacitor array of the first DAC.

18. The system of claim 12 , wherein:
the quantizer includes a comparator configured to compare the analog input signal to a reference and output a digital value for the digital signal, and
the summing junction is coupled to the comparator.

19. The system of claim 12 , wherein the summing junction combines the analog input signal combined with the second corresponding analog value from the second feedback path, the first corresponding analog value from the first feedback path, and a plurality of values from the plurality of compensation paths.

20. The system of claim 12 , wherein each ELD compensation path in the plurality of ELD compensation paths comprises a set of delay elements to provide a different delay.

21. A method comprising:
converting, at a quantizer, an analog input signal to a digital signal, wherein converting comprises:
converting, via a first feedback path, the digital signal to a first corresponding analog value for combining with the analog input signal at a summing junction, wherein the first feedback path includes a first digital to analog converter (DAC) coupled from an output of the quantizer to the summing junction that is coupled to an input of the quantizer; and
converting, by a set of second DACs in a plurality of excess loop delay (ELD) compensation paths of a second feedback path, the digital signal to a second corresponding analog value for combining with the analog input signal, wherein the plurality of excess loop delay (ELD) compensation paths are coupled to the summing junction, and wherein the plurality of excess loop delay (ELD) compensation paths compensate for excess loop delay from the second feedback path that is coupled from the output of the quantizer to input of the quantizer.

22. The method of claim 21 , further comprising programming the plurality of ELD compensation paths to compensate for different excess loop delays.

23. The method of claim 22 , further comprising associating the plurality of ELD compensation paths with coefficients that are programmable to different values.

24. The method of claim 21 , wherein an ELD compensation path in the plurality of ELD compensation paths has a different resolution then the digital signal.

25. The method of claim 21 , further comprising combining, by the summing junction, the analog input signal with the second corresponding analog value from the second feedback path, the first corresponding analog value from the first feedback path, and a plurality of values from the plurality of compensation paths.

Assignees

• Qualcomm Inc
• Qualcomm Inc

Inventors

• Dagher Elias Hani
• Yamamoto Kentaro
• Alladi Dinesh Jagannath

Classifications

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/37 Primary

  Compensation or reduction of delay or phase error · CPC title

• H03M1/34 Primary

  Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title