Generating a Wafer Inspection Process Using Bit Failures and Virtual Inspection

Patent metadata

Field	Value
Publication number	US-2016163606-A1
Application number	US-201615041016-A
Country	US
Kind code	A1
Filing date	Feb 10, 2016
Priority date	Jan 18, 2012
Publication date	Jun 9, 2016
Grant date	—

Abstract

Methods and systems for generating a wafer inspection process are provided. One method includes storing output of detector(s) of an inspection system during scanning of a wafer regardless of whether the output corresponds to defects detected on the wafer and separating physical locations on the wafer that correspond to bit failures detected by testing of the water into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected. In addition, the method includes applying defect detection method(s) to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations and generating a wafer inspection process based on the defects detected by the defect detection method(s) at the first portion of the physical locations.

First claim

What is claimed is:

1 . A system configured to generate a wafer inspection process, comprising:
an inspection subsystem configured to scan a wafer to detect defects on the wafer; and a computer subsystem configured for:
storing output of one or more detectors of the inspection system during the scanning regardless of whether the output corresponds to the defects detected on the wafer;
separating physical locations on the wafer that correspond to bit failures detected by testing of the wafer into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected;
applying one or more defect detection methods to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations; and
generating a wafer inspection process based on the defects detected by one or more defect detection methods at the first portion of the physical locations.

Assignees

• Kla Tencor Corp

Inventors

• Yong Poh Boon
• Simon George
• Du Yuezhong

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H01L22/12

  Electricity · mapped topic

• H01L22/20 Primary

  Electricity · mapped topic