Semiconductor switching device

Patent metadata

Field	Value
Publication number	US-12598781-B2
Application number	US-202318107377-A
Country	US
Kind code	B2
Filing date	Feb 8, 2023
Priority date	Feb 8, 2023
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A semiconductor device cell includes a JFET region adjacent a channel region, the JFET region defining a periphery of the semiconductor device cell. The JFET region includes a first corner region and a second corner region separated by a JFET intermediate region. A first width of the JFET intermediate region extending from an edge of the JFET intermediate region abutting a periphery of the channel region to the periphery of the semiconductor device cell is greater than a second width of the JFET region extending from an edge of at least one of the first corner region and the second corner region abutting the periphery of the channel region to the semiconductor cell periphery.

First claim

What is claimed is:

1 . A semiconductor device cell comprising:
a well region having a second conductivity type; a source region having a first conductivity type disposed adjacent to and surrounded by the well region, a channel region having the second conductivity type, disposed around and adjacent to the well region; and a JFET region abutting a periphery of the channel region and defining a semiconductor cell periphery, the JFET region having at least a first corner region and a second corner region separated by a JFET intermediate region, wherein a first width of the JFET intermediate region is greater than a second width of the JFET region, wherein the first width of the JFET intermediate region extends across the JFET intermediate region from an edge of the JFET intermediate region abutting the periphery of the channel region to the semiconductor cell periphery, wherein the second width of the JFET intermediate region extends from an edge of at least one of the first and the second corner regions abutting the periphery of the channel region to the semiconductor cell periphery, and wherein a boundary between the well region and the channel region is rectangular.

2 . The semiconductor device cell of claim 1 , wherein each of the first corner region and second corner region define a right angle.

3 . The semiconductor device cell of claim 1 , wherein the channel region defines a third corner region proximal to the first corner region.

4 . The semiconductor device cell of claim 3 , wherein the channel region defines a fourth corner region, proximal the second corner region.

5 . The semiconductor device cell of claim 1 , wherein the first width is within a range of 6 microns and 18 microns.

6 . The semiconductor device cell of claim 1 , wherein the second width is within a range of 0.07 microns and 1.4 microns.

7 . The semiconductor device cell of claim 1 , wherein the first width is at least 20% wider than the second width.

8 . A system, comprising:
a plurality of semiconductor device cells, wherein each of the plurality of semiconductor cells comprises:
a well region having a second conductivity type;
a source region having a first conductivity type disposed adjacent to and surrounded by the respective well region;
a channel region having the second conductivity type, disposed around and adjacent to the respective well region; and
a JFET region abutting a periphery of the respective channel region and defining a respective semiconductor cell periphery, the JFET region having at least a first corner region and a second corner region separated by a JFET intermediate region, wherein a first width of the JFET intermediate region is greater than a second width of the JFET region,
wherein the first width of the JFET intermediate region extends across the JFET intermediate region from an edge of the JFET intermediate region abutting the periphery of the channel region to the semiconductor cell periphery, wherein the second width of the JFET intermediate region extends from an edge of at least one of the first and the second corner regions abutting the periphery of the channel region to the semiconductor cell periphery, and wherein a boundary between the well region and the channel region is rectangular.

9 . The system of claim 8 , wherein the respective semiconductor cell periphery of each semiconductor device cell is aligned with a respective semiconductor cell periphery of an adjacent semiconductor device cell.

10 . The system of claim 8 , wherein a respective JFET intermediate region of a first semiconductor device cell and a JFET intermediate region of a second semiconductor device cell abut along a portion of the respective semiconductor cell periphery of the first and second semiconductor device cells to define a shared JFET region between the of the first and second semiconductor device cells.

11 . The system of claim 10 , wherein the respective channel regions of the first semiconductor device cell and the second semiconductor device cell are separated by the respective JFET regions of the first and second semiconductor device cells.

12 . The system of claim 10 , wherein a third width of the shared JFET region, is greater than a fourth width between the respective channel regions of the first semiconductor device cell and the second semiconductor device cell at one or more of the first corner region or the second corner region.

13 . The system of claim 12 , wherein the third width is equal to a sum of a respective first width of the first semiconductor device cell and a respective first width of the second semiconductor device cell.

14 . The system of claim 12 , wherein the fourth width is equal to a sum of a respective second width the first semiconductor device cell and a respective second width of the second semiconductor device cell.

15 . The system of claim 11 , wherein the first width is within a range of 12 microns and 36 microns.

16 . The system of claim 11 , wherein the second width is within a range of 0.14 microns and 2.8 microns.

17 . The system of claim 11 , wherein the first width is at least 20% wider that the second width.

18 . The system of claim 8 , wherein the semiconductor device cells collectively define a MOSFET.

Assignees

• Ge Aviation Systems Llc

Inventors

• Hitchcock Collin William
• Kennerly Stacey J
• Stevanovic Ljubisa D

Classifications

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D62/152

  Source regions of DMOS transistors · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title