Semiconductor device including an active region that includes a switchable current path

Patent metadata

Field	Value
Publication number	US-11189689-B2
Application number	US-201716634167-A
Country	US
Kind code	B2
Filing date	Oct 5, 2017
Priority date	Oct 5, 2017
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

A superjunction layer includes first pillars of a first conductivity type and second pillars of a second conductivity type. First wells are provided respectively on the second pillars to reach the first pillars and are of the second conductivity type. First impurity regions are provided respectively on the first wells and are of the first conductivity type. Second wells are provided respectively on the first pillars, spaced from the second pillars in a section of an active region that is perpendicular to a semiconductor layer, and are of the second conductivity type. Second impurity regions are provided respectively on the second wells and are of the first conductivity type.

First claim

The invention claimed is:

1. A semiconductor device including an active region that includes a switchable current path, comprising:
a semiconductor layer of a first conductivity type having a first surface and a second surface opposite to the first surface;
a first main electrode provided on the first surface;
a superjunction layer provided on the second surface of the semiconductor layer and consisting of a plurality of first pillars of the first conductivity type and a plurality of second pillars of a second conductivity type different from the first conductivity type in a section of the active region that is perpendicular to the second surface of the semiconductor layer, the plurality of first pillars and the plurality of second pillars being alternately aligned in an in-plane direction of the second surface, the first pillars having a constant impurity concentration and the second pillars having a constant impurity concentration;
a plurality of first wells of the second conductivity type provided respectively on the plurality of second pillars and reaching the first pillars on the superjunction layer;
a plurality of first impurity regions of the first conductivity type provided respectively on the plurality of first wells and separated from the first pillars by the first wells;
a plurality of second wells of the second conductivity type provided respectively on the plurality of first pillars and disposed spaced from the second pillars in the section;
a plurality of second impurity regions of the first conductivity type provided respectively on the plurality of second wells and separated from the first pillars by the second wells;
a control electrode opposing the first wells between the first pillars and the first impurity regions via an insulation film and opposing the second wells between the first pillars and the second impurity regions via the insulation film; and
a second main electrode joined to each of the first wells, the second wells, the first impurity regions, and the second impurity regions.

2. The semiconductor device according to claim 1 , wherein
the first wells extend to above the first pillars.

3. The semiconductor device according to claim 1 , wherein
the first wells have edges on boundaries between the first pillars and the second pillars.

4. The semiconductor device according to claim 3 , wherein
an impurity concentration in the first wells is the same as an impurity concentration in portions of the second pillars that are in contact with the first wells.

5. The semiconductor device according to claim 1 , wherein
the first pillars and the second pillars are arranged in stripes in a layout that is parallel to the second surface of the semiconductor layer.

6. The semiconductor device according to claim 1 , wherein
the second pillars have a plurality of pillar patterns as a layout that is parallel to the second surface of the semiconductor layer, and
the pillar patterns are arranged periodically along each of at least two directions.

7. The semiconductor device according to claim 6 , wherein:
the at least two directions include two directions orthogonal to each other.

8. The semiconductor device according to claim 1 , wherein
the second pillars have a plurality of pillar patterns as a layout that is parallel to the second surface of the semiconductor layer, and
the pillar patterns are arranged periodically along one direction and arranged in a staggered configuration in a direction perpendicular to the one direction.

9. The semiconductor device according to claim 1 , wherein
the second wells are arranged in stripes in a layout that is parallel to the second surface of the semiconductor layer.

10. The semiconductor device according to claim 1 , wherein
the second wells have a plurality of well patterns as a layout that is parallel to the second surface of the semiconductor layer, and
the well patterns are arranged periodically along each of at least two directions.

11. The semiconductor device according to claim 1 , wherein
the second pillars have the same width and are arranged at regular intervals in the section.

12. The semiconductor device according to claim 1 , wherein each of the second wells has a smaller width than each of the first wells in the section.

13. The semiconductor device according to claim 1 , wherein
the superjunction layer is made of silicon carbide.

14. The semiconductor device according to claim 1 , wherein
the first conductivity type is an n-type, and the second conductivity type is a p-type.

15. The semiconductor device according to claim 1 , wherein
each of the plurality of first wells includes a first contact region extending from the second main electrode to the second pillar on which the first well is provided.

16. The semiconductor device according to claim 15 , wherein
the first contact region is of the second conductivity type.

17. The semiconductor device according to claim 1 , wherein
each of the plurality of second wells includes a second contact region extending from the second main electrode to the first pillar on which the second well is provided.

18. The semiconductor device according to claim 17 , wherein
the second contact region is of the second conductivity type.

Assignees

• Mitsubishi Electric Corp

Inventors

• Furuhashi Masayuki
• Fujiwara Nobuo
• Kawabata Naoyuki

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10D64/232

  Emitter electrodes for IGBTs · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title