Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells using body region extensions

Patent metadata

Field	Value
Publication number	US-10937870-B2
Application number	US-202016789164-A
Country	US
Kind code	B2
Filing date	Feb 12, 2020
Priority date	May 23, 2016
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

First claim

The invention claimed is:

1. A device, comprising:
a plurality of device cells at least partially disposed in a semiconductor device layer, wherein each device cell of the plurality comprises:
a body region disposed near the center of the device cell;
a source region disposed adjacent to the body region of the device cell;
a channel region disposed adjacent to the source region of the device cell; and
a JFET region disposed adjacent the channel region of the device cell, wherein the JFET region has a parallel JFET width between the channel region of the device cell and a portion of a channel region of a neighboring device cell of the plurality of device cells,
wherein at least one device cell of the plurality of device cells comprises a body region extension that extends outwardly from the body region of the at least one device cell into the JFET region such that a distance between the body region extension of the at least one device cell and a region of the neighboring device cell, having a shared conductivity-type as the body region extension, is less than or equal to the parallel JFET width.

2. The device of claim 1 , wherein the semiconductor device layer is a silicon carbide (SiC) semiconductor device layer.

3. The device of claim 1 , wherein the distance between the body region extension of the at least one device cell and the region of the neighboring device cell is less than the parallel JFET width.

4. The device of claim 1 , comprising an ohmic contact disposed over at least a portion of the body region extension of the at least one device cell.

5. The device of claim 1 , wherein a width of the body region extension of the at least one device cell varies across a length of the body region extension.

6. The device of claim 1 , wherein each of the plurality of device cells has a substantially square shape.

7. The device of claim 1 , wherein each of the plurality of device cells has a hexagonal shape.

8. The device of claim 1 , wherein each of the plurality of device cells has an elongated rectangular shape.

9. The device of claim 1 , wherein each of the plurality of device cells has an elongated hexagonal shape.

10. The device of claim 1 , wherein the at least one device cell of the plurality of device cells comprises two or more device cells, wherein each device cell of the two or more device cells comprises the body region extension, and wherein the body region extension extends outwardly from the body region of each device cell, through two or more corners of the source region of each device cell, through two or more corners of the channel region of each device cell, and into the JFET region.

11. The device of claim 1 , wherein the at least one device cell comprises two or more device cells of the plurality of device cells, and each body region extension of the two or more device cells extend towards and connect to each other.

12. The device of claim 1 , wherein the at least one device cell comprises two or more device cells of the plurality of device cells, and each body region extension of the two or more device cells are oriented in substantially the same direction.

13. The device of claim 1 , wherein the at least one device cell comprises two or more device cells of the plurality of device cells, and each body region extension of the two or more device cells are oriented in different directions.

14. The device of claim 1 , wherein the body region extension of the at least one device cell does not extend through all corners of the channel region of the at least one device cell.

15. A device, comprising:
a plurality of device cells at least partially disposed in a semiconductor device layer, wherein each device cell of the plurality comprises:
a body region disposed near the center of the device cell;
a source region disposed adjacent to the body region of the device cell;
a channel region disposed adjacent to the source region of the device cell; and
a JFET region disposed adjacent the channel region of the device cell, wherein the JFET region has a parallel JFET width between the channel region of the device cell and a portion of a channel region of a neighboring device cell of the plurality of device cells,
wherein at least two device cells of the plurality of device cells comprises a body region extension that extends outwardly from the body region of each respective device cell of the at least two device cells, through two or more corners of the source region of each respective device cell of the at least two device cells, through two or more corners of the channel region of each respective device cell of the at least two device cells, and into the JFET region such that a distance between each body region extension of the at least two device cells and a region of the neighboring device cell is less than or equal to the parallel JFET width.

16. The device of claim 15 , wherein the two or more corners of the source region are opposite corners of the source region, and the two or more corners of the channel region are opposite corners of the channel region.

17. The device of claim 15 , wherein the two or more corners of the source region are adjacent corners of the source region, and the two or more corners of the channel region are adjacent corners of the channel region.

18. The device of claim 15 , wherein one or more device cells of the plurality of device cells disposed adjacent to the at least two device cells do not include respective body region extensions, and wherein the one or more device cells are shielded by the body region extension of the at least two device cells.

19. The device of claim 15 , wherein each body region extension is a body contact region extension having an ohmic contact disposed thereon.

20. The device of claim 15 , wherein the at least two device cells are in a first column of the plurality of device cells and the neighboring device cell is in a second column of the plurality of device cells that lack respective body region extensions.

Assignees

• Gen Electric

Inventors

• Bolotnikov Alexander Viktorovich
• Losee Peter Almern

Classifications

• H10P30/2042

  into crystalline silicon carbide · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D30/662

  having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region · CPC title

• H10D18/00

  Thyristors · CPC title