Semiconductor devices having channel regions with non-uniform edge

Patent metadata

Field	Value
Publication number	US-9716144-B2
Application number	US-201414577451-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 19, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A semiconductor device may include a drift region having a first conductivity type, a source region having the first conductivity type, and a well region having a second conductivity type disposed adjacent to the drift region and adjacent to the source region. The well region may include a channel region that has the second conductivity type disposed adjacent to the source region and proximal to a surface of the semiconductor device cell. The channel region may include a non-uniform edge that includes at least one protrusion.

First claim

The invention claimed is:

1. A semiconductor device structure, comprising:
a drift region having a first conductivity type;
a source region having the first conductivity type;
a well region having a second conductivity type disposed adjacent to the drift region and adjacent to the source region, wherein the well region comprises:
a channel region having the second conductivity type disposed adjacent to the source region and proximal to a surface of the semiconductor device structure,
wherein the channel region comprises a non-uniform edge, wherein the non-uniform edge comprises at least two protrusions forming a periodic non-uniform pattern along a periphery of the well region with a reduced effective channel length,
wherein the non-uniform edge region comprises a plurality of first sections and a plurality of second sections, wherein each of the plurality of first sections is longer than each of the plurality of second sections,
wherein the reduced effective channel length is designed by independently selecting at least one of: at least one of a plurality of possible shapes for the periodic non-uniform pattern; a first alignment of the plurality of the first sections relative to a second alignment of the plurality of the second sections; and a first width of at least some of the plurality of the first sections relative to a second width of at least some the plurality of the second sections,
further wherein the reduced effective length of the plurality of second sections is between approximately 0.1 μm and approximately 1 μm.

2. The semiconductor device structure of claim 1 , wherein the reduced effective length of the plurality of first sections is between approximately 0.3 μm and approximately 2 μm.

3. The semiconductor device structure of claim 1 , wherein a distance between each of the plurality of first sections is between approximately 0.1 μm and approximately 1 μm.

4. The semiconductor device structure of claim 1 , wherein a distance between each of the plurality of first sections is approximately less than or equal to a difference between a first length of each of the plurality of first sections and a second length of each of the plurality of second sections.

5. The semiconductor device structure of claim 1 , wherein the reduced effective channel length is characterized in terms of: channel length as a function of location along the edge of the channel region and a period of repetition of the pattern.

6. A semiconductor device structure, comprising:
a substrate layer;
an epitaxial layer disposed on top of the substrate layer, wherein the epitaxial layer comprises:
a source region implanted into a surface of the epitaxial layer and having a first conductivity type; and
a well region implanted into the surface of the epitaxial layer adjacent the source region and having a second conductivity type,
wherein the well region comprises a non-uniform edge that defines a channel region with the non-uniform edge,
wherein the non-uniform edge comprises plurality of first sections and a plurality of second sections, wherein each of the plurality of first sections is longer than each of the plurality of second sections,
wherein the non-uniform edge comprises at least two protrusions forming a periodic non-uniform pattern along a periphery of the well region with a reduced effective channel length,
wherein the effective channel length is designed by independently selecting at least one of: at least one of a plurality of possible shapes for the periodic non-uniform pattern; a first alignment of the plurality of the first sections relative to a second alignment of the plurality of the second sections; and a first width of at least some the plurality of the first sections relative to a second width of at least some the plurality of the second sections,
further wherein the reduced effective length of the plurality of second sections is between approximately 0.1 μm and approximately 1 μm.

7. The semiconductor device structure of claim 6 , comprising:
an insulator disposed on the epitaxial layer, the well region, and the source region; and
a gate electrode disposed on the insulator.

8. The semiconductor device structure of claim 6 , wherein the plurality of first sections and the plurality of second sections are configured to prevent leakage current density below 1 mA/cm2 at a maximum rated blocking voltage due to drain-induced barrier lowering (DIBL).

9. The semiconductor device structure of claim 6 , wherein the plurality of first regions is configured to maintain approximately the same electric field along a junction field-effect transistor (JFET) region in the epitaxial layer between any opposing section of the plurality of first and second sections during blocking operation of the semiconductor device structure.

10. The semiconductor device structure of claim 6 , wherein a first total charge of the plurality of first sections is greater than or equal to a second total charge bounded by plurality of first sections when the semiconductor device structure is in a blocking state.

11. The semiconductor device structure of claim 6 , wherein the doping concentration of the channel region with respect to the epitaxial layer corresponds to:
W _long* N ch ≧W _short* N epi

where W_long corresponds to a width of one of the plurality of first sections, W_short corresponds to a width of one of the plurality of second sections, N ch corresponds to a doping concentration of the channel region, and N epi corresponds to a doping concentration of the epitaxial layer.

12. The semiconductor device structure of claim 11 , wherein the width of the one of the plurality of first sections is approximately between 0.1 μm and 2 μm, wherein the length of the one of the plurality of first sections is approximately between 0.1 μm and 2 μm.

13. The semiconductor device structure of claim 11 , wherein N epi is within a first range between 1e15 cm-3 and 1e17 cm-3, and wherein N ch is within a second range between 1e16 cm-3 and 1e19 cm-3.

14. The semiconductor device structure of claim 6 , wherein a width of one of the plurality of second sections is less than or equal to a difference between a length of one of the plurality of first sections and a length of the one of the plurality of second sections.

15. The semiconductor device structure of claim 6 , wherein the reduced effective channel length is characterized in terms of: channel length as a function of location along the edge of the channel region and a period of repetition of the pattern.

Assignees

• Gen Electric

Inventors

• Bolotnikov Alexander Viktorovich
• Losee Peter Almern

Classifications

• H01L29/7802

  Electricity · mapped topic

• H01L29/7395

  Electricity · mapped topic

• H01L29/66333

  Electricity · mapped topic

• H01L29/0865

  Electricity · mapped topic

• H01L29/1037 Primary

  Electricity · mapped topic