MOSFET in sic with self-aligned lateral MOS channel

Patent metadata

Field	Value
Publication number	US-11444192-B2
Application number	US-201917256952-A
Country	US
Kind code	B2
Filing date	Jun 28, 2019
Priority date	Jun 29, 2018
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions (7) comprising an access region (7a) and a JFET region (7b) defining the length of the MOS channel (17), and wherein the access region (7a) and the JFET region (7b) are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel (17) is defined by simultaneous creating n-type regions on both sides of the channel (17) using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.

First claim

The invention claimed is:

1. A method of manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising:
an n+substrate ( 1 ),
an n drift layer ( 3 ) in contact with the n+substrate ( 1 ),
the method comprising:
forming a p type buried grid ( 4 ) in contact with the n drift layer ( 3 ),
forming a p-well ( 6 ) above the p type buried grid ( 4 ),
forming simultaneously formed n type regions ( 7 ) comprising an access region ( 7 a ) and a JFET region ( 7 b ) that are laterally self-aligned and have an intermediate part of the p-well ( 6 ) between the access region ( 7 a ) and the JFET region ( 7 b );
forming an n+source ( 8 ) in contact with the p-well ( 6 ) and the access region ( 7 a ),
forming a p body ( 9 ) for a body diode circuit in contact with the p-well ( 6 ) and the p type buried grid ( 4 ),
forming an insulating gate oxide ( 10 ) on a portion of the n+source ( 8 ), the access region ( 7 a ), the intermediate part of the p-well ( 6 ), and the JFET region ( 7 b ),
forming a gate contact ( 11 ) on the insulating gate oxide ( 10 ),
forming an isolation layer ( 12 ) on the gate contact ( 11 ),
forming a source contact ( 13 ) for a MOSFET circuit in contact with the n+source ( 8 ),
forming a body diode contact ( 14 ) for the body diode circuit in contact with the p body ( 9 ), and
forming a drain contact ( 15 ) in contact with the n+substrate ( 1 ),
wherein the simultaneously formed access region ( 7 a ) and JFET region ( 7 b ), which are laterally self-aligned, have the intermediate part of the p-well ( 6 ) between the access region ( 7 a ) and the JFET region ( 7 b ), and are in contact with the gate oxide ( 10 ), define a MOS channel ( 17 ),
wherein the access region ( 7 a ) is in contact with the n+source ( 8 ),
wherein the JFET region ( 7 b ) is in contact with the n drift layer ( 3 ) or with an optional n layer ( 5 ) between the n drift layer ( 3 ) and the JFET region ( 7 b ), and
wherein the access region ( 7 a ) and the JFET region ( 7 b ) in the simultaneously formed n type regions ( 7 ) are formed by ion implantation into the p-well ( 6 ) by using one masking step, wherein one of the following steps is carried out:
i. forming the p-well ( 6 ) by a process involving ion implantation and the simultaneously formed n type regions ( 7 ) being implanted to such a depth that a part of the p-well ( 6 ) under the access region ( 7 a ) remains, or
ii. forming the p-well ( 6 ) by epitaxial growth not involving ion implantation, wherein at least one selected from a p-well implant ( 6 b ) and the p type buried grid ( 4 ) is disposed between the n drift layer ( 3 ) and a region consisting of the p-well ( 6 ) as well as the access region ( 7 a ).

2. The method according to claim 1 , wherein the MOSFET comprises an n+buffer layer ( 2 ) between the n+substrate ( 1 ) and the n drift layer ( 3 ).

3. The method according to claim 1 , wherein the isolation layer ( 12 ) also is between the source contact ( 13 ) and the body diode contact ( 14 ).

4. The method according to claim 1 , wherein the source contact ( 13 ) and the body diode contact ( 14 ) are connected.

5. The method according to claim 1 , wherein the source contact ( 13 ) and the body diode contact ( 14 ) are connected by a thick metallization ( 16 ).

6. The method according to claim 1 , wherein the source contact ( 13 ) and the body diode contact ( 14 ) are not connected.

7. The method according to claim 1 , wherein the part of the p-well ( 6 ) which is not the MOS channel ( 17 ) has a doping concentration which is different from the intermediate part of the p-well ( 6 ) which is the MOS channel ( 17 ).

8. The method according to claim 1 , wherein the p-well ( 6 ) has a higher doping concentration towards the lower part of the p-well ( 6 ).

9. The method according to claim 1 , wherein the access region ( 7 a ) has a doping concentration less than 1e17/cm3.

10. A MOSFET with lateral channel in SiC, said MOSFET comprising:
an n+substrate ( 1 ),
an n drift layer ( 3 ) in contact with the n+substrate ( 1 ),
a p type buried grid ( 4 ) in contact with the n drift layer ( 3 ),
a p-well ( 6 ) above the p type buried grid ( 4 ),
simultaneously formed n type regions ( 7 ) comprising an access region ( 7 a ) and a JFET region ( 7 b ) that are laterally self-aligned and have an intermediate part of the p-well ( 6 ) disposed between the access region ( 7 a ) and the JFET region ( 7 b ),
an n+source ( 8 ) in contact with the p-well ( 6 ) and the access region ( 7 a ),
a p body ( 9 ) for a body diode circuit in contact with the p-well ( 6 ) and the p type buried grid ( 4 ),
an insulating gate oxide ( 10 ) on a portion of the n+source ( 8 ), the access region ( 7 a ), the intermediate part of the p-well ( 6 ), and the JFET region ( 7 b ),
a gate contact ( 11 ) on the insulating gate oxide ( 10 ),
an isolation layer ( 12 ) on the gate contact ( 11 ),
a source contact ( 13 ) for a MOSFET circuit in contact with the n+source ( 8 ),
a body diode contact ( 14 ) for the body diode circuit in contact with the p body ( 9 ), and
a drain contact ( 15 ) in contact with the n+substrate ( 1 ),
wherein the simultaneously formed access region ( 7 a ) and JFET region ( 7 b ), which are laterally aligned and have the intermediate part of the p-well ( 6 ) between the access region ( 7 a ) and the JFET region ( 7 b ), define a MOS channel ( 17 ),
wherein the access region ( 7 a ) is in contact with the n+source ( 8 ),
wherein the JFET region ( 7 b ) is in contact with the n drift layer ( 3 ) or with an optional n layer ( 5 ) between the n drift layer ( 3 ) and the JFET region ( 7 b ),
wherein the access region ( 7 a ) and the JFET region ( 7 b ) in the simultaneously formed n type regions ( 7 ) have the same doping concentration and define the length of the MOS channel ( 17 ) with a tolerance of ±50 nm or less, and
wherein the MOSFET satisfies one of:
iii. the p-well ( 6 ) is made by a process involving ion implantation and the simultaneously formed n type regions ( 7 ) are implanted to such a depth that a part of the p-well ( 6 ) under the access region ( 7 a ) remains, or
iv. the p-well ( 6 ) is made by epitaxial growth not involving ion implantation, wherein at least one selected from a p-well implant ( 6 b ) and the p type buried grid ( 4 ) is disposed between the n drift layer ( 3 ) and a region consisting of the p-well ( 6 ) as well as the access region ( 7 a ).

11. The MOSFET according to claim 10 , wherein the length of the MOS channel ( 17 ) is defined with a tolerance of ±30 nm or less.

12. The MOSFET according to claim 10 , wherein the MOSFET comprises an n+buffer layer ( 2 ) between the n+substrate ( 1 ) and the n drift layer ( 3 ).

13. The MOSFET according to claim 10 , wherein the isolation layer ( 12 ) also is between the source contact ( 13 ) and the body diode contact ( 14 ).

14. The MOSFET according to claim 10 , wherein the source contact ( 13 ) and the body diode contact ( 14 ) are connected.

15. The MOSFET according to claim 10 , wherein the source contact ( 13 ) and the body diode contact ( 14 ) are connected by a thick metallization ( 16 ).

16. The MOSFET according to claim 10 , wherein the source contact ( 13 ) and the body diode contact ( 14 ) are not connected.

17. The MOSFET according to claim 10 , wherein the part of the p well ( 6 ) which is not the MOS channel ( 17 ) has a doping concentration which is different from the intermediate part of the p-well ( 6 ) which is the MOS channel ( 17

Assignees

• Ascatron Ab
• Ii Vi Delaware Inc

Inventors

• Schöner Adolf
• Reshanov Sergey
• Thierry-Jebali Nicolas
• Elahipanah Hossein

Classifications

• H10P30/22

  using masks · CPC title

• H10D12/031

  of IGBTs · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P30/2042

  into crystalline silicon carbide · CPC title

• H10D84/146 Primary

  the built-in components being Schottky barrier diodes · CPC title