Method for producing a through semiconductor via connection

Patent metadata

Field	Value
Publication number	US-2020006142-A1
Application number	US-201916456833-A
Country	US
Kind code	A1
Filing date	Jun 28, 2019
Priority date	Jul 2, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.

First claim

What is claimed is:

1 . A method of producing a through semiconductor via (TSV) connection in a stack comprising a first semiconductor die and a second semiconductor die or a carrier substrate, the first die being bonded to the second die or to the carrier substrate, the first die comprising:
a semiconductor substrate portion having a front side and a back side; on the front side of the substrate portion, at least one well of semiconductor material of a first doping type implanted in an area of the substrate portion, the area being formed of semiconductor material of a second doping type opposite the first doping type; one or more fins of material of the first doping type extending outward from the at least one well; a conductor that is electrically coupled to at least one of the one or more fins extending outward from the at least one well, the method comprising: producing an opening for the TSV connection, wherein the opening is produced by an etching process that stops in the at least one well of semiconductor material of the first type; and filling the opening with an electrically conductive material, wherein after filling of the opening, an electrical connection is established from the TSV connection to the conductor, through the at least one well and through the at least one of the one or more fins.

2 . The method according to claim 1 , wherein the opening is etched through the backside of the substrate portion, after bonding the first die to the second die or to the carrier substrate.

3 . The method according to claim 1 , wherein the opening is etched after bonding the first die to the second die, and wherein the opening is etched through the second die.

4 . The method according to claim 1 , wherein the conductor is formed as a wrap-around contact layer so as to contact a top and sidewalls of the at least one fin.

5 . The method according to claim 1 , wherein the filling includes seed layer deposition.

6 . The method according to claim 1 , wherein the at least one well comprises an n-well and the at least one fin comprises an n-doped fin, and wherein the TSV connection is electrically connected to the conductor of an intermediate metallization of the first die via the n-well and the n-doped fin.

7 . The method according to claim 1 , wherein the at least one well comprises an n-well included in the front side of the semiconductor substrate portion.

8 . The method according to claim 1 , further comprising, prior to filling the opening with a conductive material:
producing a dielectric liner on the sidewalls of the opening, followed by:
depositing a reactive material in the opening, and
enabling a reaction to take place between the reactive material and the semiconductor material in the at least one well, so as to form at the bottom of the opening a portion of reacted material having higher conductivity than the material of the at least one well prior to the reaction.

9 . The method according to claim 8 , wherein the material of the dielectric liner comprises one of SiO 2 , SiCO, SiN, and SiCN.

10 . The method according to claim 8 , wherein the dielectric liner is conformally deposited with atomic layer deposition.

11 . The method according to claim 8 , wherein dielectric liner is removed at the bottom of the opening using a plasma etch.

12 . A package of interconnected semiconductor dies, comprising at least one first die bonded to a second die, wherein at least the first die of the package comprises:
a semiconductor substrate portion; at least one well of semiconductor material of a first doping type implanted in an area of the substrate portion, the area being formed of semiconductor material of a second doping type opposite the first doping type; one or more fins of material of the first doping type extending outward from the at least one well; at least one conductor that is electrically coupled to at least one of the one or more fins extending outward from the at least one well, wherein:
the package comprises one or more TSV connections for interconnecting the dies of the package, and
at least one TSV connection ends in the at least one well of the first die, so that the at least one TSV connection is electrically connected to the conductor of the first die through the at least one well and through the at least one of the one or more fins.

13 . The package according to claim 12 , wherein the TSV connection is formed through the semiconductor substrate portion of the first die.

14 . The package according to claim 12 , wherein the TSV connection is formed through the second die.

15 . The package according to claim 12 , further comprising, at the end of the TSV connection, a portion of material having higher conductivity than the material of the at least one well.

Assignees

• Imec Vzw

Inventors

• Hiblot Gaspard
• Van Huylenbroeck Stefaan
• Van Der Plas Geert

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title