Three layer stack structure

Patent metadata

Field	Value
Publication number	US-2016315071-A1
Application number	US-201514804261-A
Country	US
Kind code	A1
Filing date	Jul 20, 2015
Priority date	Apr 23, 2015
Publication date	Oct 27, 2016
Grant date	—

Abstract

Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level molding and fan out structure, and a second level molding and fan out structure between the first and third levels. The second level molding and fan out structure includes back-to-back facing die, with a front surface of each die bonded to a redistribution layer.

First claim

1 . A vertical stack system in package (SiP) comprising:
a first level die encapsulated in a first level molding compound; a first redistribution layer (RDL) on the encapsulated first level die; a second level die stack including a pair of back-to-back stacked die on the first RDL and encapsulated in a second level molding compound; a second RDL on the encapsulated second level die stack; a third level die on the second RDL and encapsulated in a third level molding compound, wherein the third level die is back facing toward the second RDL; and a third RDL on the encapsulated third level die.

2 . The vertical stack SiP of claim 1 , wherein the third RDL is directly on a stud bump of the third level die.

3 . The vertical stack SiP of claim 1 , wherein the third RDL is directly on a contact pad of the third level die.

4 . The vertical stack SiP of claim 1 , wherein the third level die is attached to the second RDL with a die attach film.

5 . The vertical stack SiP of claim 1 , wherein the first level die is front facing toward the first RDL and the first RDL is directly on a conductive bump of the first level die.

6 . The vertical stack SiP of claim 1 , wherein the pair of back-to-back stacked die includes a first-second level die bonded to the first RDL, and a second-second level die, wherein the second RDL is on the second-second level die.

7 . The vertical stack SiP of claim 6 , wherein the first-second level die is bonded to the first RDL with solder.

8 . The vertical stack SiP of claim 7 , wherein the second RDL is directly on a stud bump of the second-second level die.

9 . The vertical stack SiP of claim 6 , further comprising a plurality of second level conductive pillars extending from the first RDL to the second RDL, wherein the plurality of second level conductive pillars are encapsulated with the second level molding compound.

10 . The vertical stack SiP of claim 9 , further comprising a plurality of third level conductive pillars extending from the second RDL to the third RDL, wherein the plurality of third level conductive pillars are encapsulated with the third level molding compound.

11 . The vertical stack SiP of claim 10 , further comprising a plurality of conductive bumps on an opposite side of the third RDL from the third level die.

12 . The vertical stack SiP of claim 10 , further comprising:
a plurality of first level conductive pillars extending through the first level molding compound; and a second package on the first level molding compound, and electrically connected with the plurality of first level conductive pillars.

13 . A vertical stack system in package (SiP) comprising:
a first level volatile memory die encapsulated in a first level molding compound; a first redistribution layer (RDL) on the encapsulated first level volatile memory die; a second level non-volatile memory die stack including a pair of back-to-back stacked non-volatile memory die on the first RDL and encapsulated in a second level molding compound; a second RDL on the encapsulated second level non-volatile memory die stack; a third level active die on the second RDL and encapsulated in a third level molding compound; and a third RDL on the encapsulated third level active die.

14 . The vertical stack SiP of claim 13 , further comprising a plurality of the first level volatile memory die encapsulated in the first level molding compound, wherein the first RDL is on the plurality of encapsulated first level volatile memory die.

15 . The vertical stack SiP of claim 13 , wherein:
the first level volatile memory die is a DRAM die; the back-to-back stacked non-volatile memory die are NAND die; and the third level active die is an SoC die.

16 - 20 . (canceled)

Assignees

• Apple Inc

Inventors

• Zhai Jun
• Hu Kunzhong

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title