Substrate and preparation method thereof, integrated passive device, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-12581979-B2
Application number	US-202218021813-A
Country	US
Kind code	B2
Filing date	Mar 31, 2022
Priority date	Mar 31, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

Provided are a substrate, a method for preparing the substrate, an integrated passive device, and an electronic apparatus. The method for preparing the substrate includes: providing a base substrate including at least one blind via, wherein the base substrate includes a first surface and a second surface disposed oppositely, a blind via extends from a first surface side to interior of the base substrate, and an aperture of the blind via gradually decreases in a direction from the first surface to the second surface; forming a connection electrode in the blind via; thinning the base substrate along a direction from the second surface to the first surface, wherein the blind via on the thinned base substrate forms a via hole penetrating the base substrate.

First claim

The invention claimed is:

1 . A method for preparing a substrate, comprising:
providing a base substrate comprising at least one blind via, wherein the base substrate comprises a first surface and a second surface disposed oppositely, a blind via extends from the first surface to interior of the base substrate, an aperture of the blind via gradually decreases in a direction from the first surface to the second surface; forming a connection electrode in the blind via; and thinning the base substrate along a direction from the second surface to the first surface, wherein the blind via on the base substrate after thinning is performed forms a via hole penetrating the base substrate; wherein the thinning the base substrate along a direction from the second surface to the first surface comprises: bonding a temporary carrier on the first surface of the base substrate, and thinning the base substrate along the direction from the second surface to the first surface; and polishing a thinned side of the base substrate by adopting a chemical physical polishing process; wherein before the bonding a temporary carrier on the first surface of the base substrate, the method further comprises: forming a front conductive film layer on the first surface of the base substrate; the bonding a temporary carrier on the first surface of the base substrate comprises: bonding the temporary carrier on the front conductive film layer on the first surface of the base substrate; after the polishing a thinned side of the base substrate by adopting a chemical physical polishing process, the method further comprises: forming a back conductive film layer on a polished surface of the base substrate; and removing the temporary carrier; wherein the front conductive film layer and the back conductive film layer are electrically connected through the connection electrode.

2 . The method according to claim 1 , wherein the forming a connection electrode in the blind via comprises:
depositing a conductive thin film on the first surface of the base substrate, to enable the conductive thin film to be formed on the first surface and a blind via wall, wherein the conductive thin film serves as a seed layer; forming an electroplated layer on the conductive thin film; removing a conductive thin film and an electroplated layer located on the first surface, and retaining a seed layer and an electroplated layer located in the blind via, wherein the electroplated layer located in the blind via is the connection electrode.

3 . The method according to claim 2 , wherein the depositing a conductive thin film on the first surface of the base substrate comprises: depositing the conductive thin film on the first surface of the base substrate by adopting a magnetron sputtering process.

4 . The method according to claim 2 , wherein the removing a conductive thin film and an electroplated layer located on the first surface comprises: removing the conductive thin film and the electroplated layer on the first surface of the base substrate by adopting a chemical physical polishing process.

5 . The method according to claim 1 , wherein the provided base substrate comprising at least one blind via has a thickness of 400 microns to 800 microns, a depth of the blind via is 100 microns to 300 microns, a thickness of the thinned base substrate is 100 microns to 300 microns, and an aperture size of the blind via is less than 150 microns.

6 . The method according to claim 1 , wherein before the providing a base substrate comprising at least one blind via, the method further comprises:
forming the at least one blind via on the first surface of the base substrate by laser modification and wet etching.

7 . The method according to claim 1 , wherein a material of the base substrate is glass.

8 . A substrate prepared using the method according to claim 1 , comprising: the base substrate comprising the first surface and the second surface disposed oppositely; wherein the via hole is provided on the base substrate, and the connection electrode is provided in the via hole.

9 . The substrate according to claim 8 , wherein a minimum aperture size of the via hole is 20 microns to 50 microns, and a maximum aperture size of the via hole is 40 microns to 60 microns.

10 . An integrated passive device, comprising the substrate according to claim 8 .

11 . An electronic apparatus, comprising the integrated passive device according to claim 10 .

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wu Yifan
• Li Yue
• Xiao Yuelei
• Han Kidong
• An Qichang
• Feng Yulin
• Cao Xue
• Chang Wenbo
• Zhou Yi
• Wang Lihui
• Wei Qiuxu
• Qu Feng

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/65 Primary

  Shapes or dispositions of interconnections · CPC title