Semiconductor device and method of forming protection and support structure for conductive interconnect structure

Patent metadata

Field	Value
Publication number	US-9484259-B2
Application number	US-201113239080-A
Country	US
Kind code	B2
Filing date	Sep 21, 2011
Priority date	Sep 21, 2011
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a plurality of contact pads;
forming a first insulating layer over the semiconductor wafer and contact pads;
forming an under bump metallization layer over the contact pads and the first insulating layer;
forming a plurality of bumps over the under bump metallization layer;
forming a second insulating layer over the semiconductor wafer to completely cover the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps;
etching the second insulating layer to remove a portion of the second insulating layer covering the upper surface of the bumps and a first portion of the sidewall of the bumps, while maintaining coverage of the second insulating layer over a second portion of the sidewall of the bumps and the sidewall of the under bump metallization layer to provide structural support for the bumps and form an area over the second insulating layer and between the bumps devoid of material; and
singulating the semiconductor wafer with the area over the second insulating layer and between the bumps devoid of material.

2. The method of claim 1 , wherein after removing the portion of the second insulating layer a thickness of the second insulating layer at the sidewall of the bumps is greater than one fourth of a height of the bumps.

3. The method of claim 1 , wherein removing the portion of the second insulating layer further includes removing the second insulating layer from over a surface of the first insulating layer outside a footprint of the bumps.

4. The method of claim 1 , wherein forming the bumps includes forming cylindrical bumps.

5. The method of claim 1 , wherein forming the bumps includes forming bumps with a rectangular cross-section.

6. The method of claim 1 , wherein removing the portion of the second insulating layer leaves a sloped surface of the second insulating layer around the bumps.

7. The method of claim 1 , wherein removing the portion of the second insulating layer includes reducing a thickness of the second insulating layer.

Assignees

• Lin Yaojian
• Chen Kang
• Fang Jianmin
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Chen Kang
• Fang Jianmin

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/01955

  by using masks · CPC title