Sensor packaging using a low-temperature through-silicon via (TSV) technology and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10304757-B2
Application number	US-201615573955-A
Country	US
Kind code	B2
Filing date	May 13, 2016
Priority date	May 14, 2015
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

A method for manufacturing a sensor packaging according to an exemplary embodiment of the present disclosure includes: forming a via hole penetrating a main substrate by etching each of both surfaces of the main substrate; forming an insulating layer on a wall surface of the via hole and the both surfaces of the main substrate; combining a sub-substrate on which a metallic seed layer and a bonding layer having a pattern for exposing a part of the seed layer are laminated with the main substrate; forming a filling layer configured to cover an upper surface of the main substrate by filling metal in the via hole; and removing the sub-substrate from the main substrate.

First claim

The invention claimed is:

1. A method for manufacturing a sensor packaging, the method comprising:
forming a via hole penetrating a main substrate by etching each of both surfaces of the main substrate;
forming an insulating layer on a wall surface of the via hole and the both surfaces of the main substrate;
combining a sub-substrate on which a metallic seed layer and a bonding layer having a pattern for exposing a part of the seed layer are laminated with the main substrate;
forming a filling layer configured to cover an upper surface of the main substrate by filling metal in the via hole; and
removing the sub-substrate from the main substrate.

2. The method for manufacturing a sensor packaging of claim 1 , wherein the forming of a via hole includes:
forming the via hole by performing Deep Reactive Ion Etching (DRIE) to each of an upper surface and a lower surface of the main substrate.

3. The method for manufacturing a sensor packaging of claim 1 , wherein the wall surface of the via hole is formed as a bent slanted surface.

4. The method for manufacturing a sensor packaging of claim 1 , wherein the forming of an insulating layer includes:
forming the insulating layer using a polymer which is available for deposition at room temperature.

5. The method for manufacturing a sensor packaging of claim 4 , wherein the polymer includes parylene.

6. The method for manufacturing a sensor packaging of claim 1 , wherein the combining of a sub-substrate with the main substrate includes:
preparing the sub-substrate on which the seed layer is deposited in advance;
forming the bonding layer on the seed layer of the sub-substrate;
forming the pattern by etching a part of the bonding layer; and
combining the sub-substrate with the main substrate by aligning and bonding the bonding layer of the sub-substrate and the insulating layer of the main substrate such that the pattern matches with the via hole.

7. The method for manufacturing a sensor packaging of claim 6 , wherein the bonding layer is formed of a polymer including at least one of parylene, polydimethylsiloxane (PDMS), polymethyl methacrylate (PMMA), SU8, photoresist, and the like.

8. The method for manufacturing a sensor packaging of claim 6 , wherein the pattern is formed after or at the same time when the bonding layer is deposited on the seed layer.

9. The method for manufacturing a sensor packaging of claim 1 , wherein the main substrate includes a silicon wafer, and the sub-substrate includes a handle wafer or a handle tape.

Assignees

• Univ Hanyang Ind Univ Coop Found

Inventors

• Yoon Sang Won

Classifications

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P50/242

  of Group IV materials · CPC title