Nonvolatile memory devices and memory systems including the same

Patent metadata

Field	Value
Publication number	US-12581919-B2
Application number	US-202318322714-A
Country	US
Kind code	B2
Filing date	May 24, 2023
Priority date	Sep 6, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

There is provided a nonvolatile memory device having improved crack detection reliability. The nonvolatile memory device comprises word lines that extend in a first direction, cell contact plugs that are electrically connected to the word lines and extend in a second direction intersecting the first direction, a net crack detection circuit that is on the word lines and is not in contact with the word lines, and a ring crack detection circuit that is on the word lines and is not in contact with the word lines, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, the ring crack detection circuit includes a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction, and a second crack detection metal wiring that extends in the third direction.

First claim

What is claimed is:

1 . A nonvolatile memory device comprising:
a plurality of word lines that extend in a first direction; a plurality of cell contact plugs that are electrically connected to the plurality of word lines and extend in a second direction intersecting the first direction; a net crack detection circuit that is on the plurality of word lines and is not in contact with the plurality of word lines; and a ring crack detection circuit that is on the plurality of word lines and is not in contact with the plurality of word lines, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, the ring crack detection circuit includes a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction, and a second crack detection metal wiring that extends in the third direction, and the first crack detection metal wiring is on the plurality of word lines and is not in contact with the plurality of word lines, and the second crack detection metal wiring is in the peripheral circuit region.

2 . The nonvolatile memory device of claim 1 , wherein the plurality of word lines and the plurality of cell contact plugs are in a cell region,
wherein the peripheral circuit region and the cell region are connected to each other in the second direction, wherein a contact portion between the peripheral circuit region and the cell region is defined as a bonding region, and wherein the bonding region includes an uppermost end of the peripheral circuit region and an uppermost end of the cell region.

3 . The nonvolatile memory device of claim 2 , wherein the net crack detection circuit comprises:
a first crack detection upper bonding metal at the uppermost end of the peripheral circuit region; and a second crack detection upper bonding metal at the uppermost end of the cell region, and wherein the first crack detection upper bonding metal and the second crack detection upper bonding metal are electrically connected to each other.

4 . The nonvolatile memory device of claim 1 , further comprising:
a plurality of metal wirings electrically connected to the plurality of cell contact plugs and stacked in the second direction, wherein the first crack detection metal wiring is between respective ones of the plurality of metal wirings.

5 . The nonvolatile memory device of claim 1 , wherein the peripheral circuit region comprises:
a plurality of circuit elements; and a plurality of metal wirings electrically connected to the plurality of circuit elements and stacked in the second direction, and wherein the second crack detection metal wiring is between respective ones of the plurality of metal wirings.

6 . The nonvolatile memory device of claim 1 , wherein the first crack detection metal wiring and the second crack detection metal wiring are not electrically connected to each other.

7 . The nonvolatile memory device of claim 1 , wherein the net crack detection circuit comprises:
a plurality of metal wirings electrically connected to the crack detection transistor and stacked in the second direction; and a first crack detection upper bonding metal electrically connected to the plurality of metal wirings.

8 . The nonvolatile memory device of claim 7 , wherein the net crack detection circuit further comprises a second crack detection upper bonding metal that is in a cell region,
wherein the cell region includes the plurality of word lines and the plurality of cell contact plugs, and wherein the first crack detection upper bonding metal and the second crack detection upper bonding metal are electrically connected.

9 . A nonvolatile memory device comprising:
a substrate that extends in a first direction; a plurality of lower metal patterns spaced apart from the substrate in the first direction; a plurality of I/O contact plugs that are electrically connected to the plurality of lower metal patterns and extend in a second direction intersecting the first direction; and a net crack detection circuit and a ring crack detection circuit between respective ones of the plurality of I/O contact plugs, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, and wherein the ring crack detection circuit includes: a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction; and a second crack detection metal wiring that extends in the third direction.

10 . The nonvolatile memory device of claim 9 , wherein the first crack detection metal wiring and the second crack detection metal wiring are not electrically connected to each other.

11 . The nonvolatile memory device of claim 9 , wherein the net crack detection circuit comprises:
a plurality of metal wirings electrically connected to the crack detection transistor and stacked in the second direction; and a first crack detection upper bonding metal electrically connected to the plurality of metal wirings.

12 . The nonvolatile memory device of claim 11 , wherein the net crack detection circuit further comprises a second crack detection upper bonding metal in a cell region,
wherein the cell region includes the substrate, the plurality of lower metal patterns, and the plurality of I/O contact plugs, and wherein the first crack detection upper bonding metal and the second crack detection upper bonding metal are electrically connected.

13 . A memory system comprising:
a nonvolatile memory device; and a controller that is configured to control the nonvolatile memory device, wherein the nonvolatile memory device comprises: a plurality of word lines that extend in a first direction; a plurality of cell contact plugs that are electrically connected to the plurality of word lines and extend in a second direction intersecting the first direction; a net crack detection circuit that is on the plurality of word lines and is not in contact with the plurality of word lines; and a ring crack detection circuit that is on the plurality of word lines and is not in contact with the plurality of word lines, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, wherein the ring crack detection circuit includes: a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction; and a second crack detection metal wiring that extends in the third direction, wherein the first crack detection metal wiring is on the plurality of word lines and is not in contact with the plurality of word lines, and wherein the second crack detection metal wiring is in the peripheral circuit region.

14 . The memory system of claim 13 , wherein the plurality of word lines and the plurality of cell contact plugs are in a cell region,
wherein the peripheral circuit region and the cell region are connected to each other in the second direction, wherein a contact portion between the peripheral circuit region and the cell region is defined as a bonding region, and wherein the bonding region includes an uppermost end of the peripheral circuit region and an uppermost end of the cell region.

15 . The memory system of claim 14 , wherein the net crack detection circuit comprises:
a first crack detection upper bonding metal at the uppermost end of the peripheral circuit region; and a second crack detection upper bonding metal at the uppermost end of t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Do Hyung
• Kim Ji Young
• Kim Ji Won
• Sung Suk Kang
• Yang Woo Sung

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title