Memory device and manufacturing method therefor

Patent metadata

Field	Value
Publication number	US-10748915-B2
Application number	US-201815909568-A
Country	US
Kind code	B2
Filing date	Mar 1, 2018
Priority date	Sep 14, 2017
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.

First claim

What is claimed is:

1. A memory device comprising:
a plurality of elements that include three-dimensional arranged memory cells;
a transistor electrically connected to at least one of the plurality of elements;
an inspection pad electrically connected in series to at least one of the plurality of elements through the transistor; and
a wiring electrically connected to the inspection pad and to a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state,
wherein the wiring is provided in a wiring layer that is a different layer than the inspection pad in a stacking direction of a plurality of word lines of the three-dimensional arranged memory cells.

2. The memory device according to claim 1 ,
wherein the inspection pad is provided in a wiring layer that is a different layer than the plurality of elements in the stacking direction of the plurality of word lines of the three-dimensional arranged memory cells.

3. The memory device according to claim 1 , further comprising:
a substrate on which the plurality of elements are provided,
wherein the inspection pad and the gate of the transistor are electrically connected to the substrate through the wiring.

4. The memory device according to claim 1 , further comprising:
a gate pad provided in a wiring layer in which the inspection pad is provided, and connected to the gate of the transistor,
wherein the wiring is electrically connected to the gate pad.

5. A manufacturing method for forming a memory device, the method comprising:
forming a plurality of elements that include three-dimensional arranged memory cells, a transistor electrically connected to at least one of the plurality of elements, and an inspection pad connected in series to at least one of the plurality of elements through the transistor;
turning the transistor to an ON state and inspecting the presence or absence of electrical connection or current-voltage characteristics between the at least one of the plurality of elements and at least one other element through the inspection pad;
forming a wiring electrically connected to the inspection pad and a gate of the transistor, and
turning the transistor to an OFF state by supplying a predetermined bias to the inspection pad and the gate of the transistor through the wiring and inspecting a memory cell,
wherein the wiring is formed in a wiring layer that is a different layer than the inspection pad in a stacking direction of a plurality of word lines of the three-dimensional arranged memory cells.

6. The manufacturing method according to claim 5 ,
wherein the inspection pad is formed in a wiring layer that is a different layer than the plurality of elements in the stacking direction of the plurality of word lines of the three-dimensional arranged memory cells.

7. The manufacturing method according to claim 5 , further comprising:
forming a substrate on which the plurality of elements are provided; and
electrically connecting the inspection pad and the gate of the transistor to the substrate through the wiring.

8. The manufacturing method according to claim 5 , further comprising:
forming a gate pad in a wiring layer in which the inspection pad is formed; and
connecting the gate pad to the gate of the transistor,
wherein the wiring is electrically connected to the gate pad.

9. A memory device comprising:
a first stacked body including a plurality of first electrode layers that extend in a first direction and are stacked in a second direction intersecting the first direction; and
a semiconductor pillar extending through the plurality of first electrode layers in the second direction,
wherein the plurality of first electrode layers include a plurality of first layers and a plurality of second layers located between the first layers in the second direction,
the plurality of first layers are electrically connected to a substrate through a common first conductor, the first conductor being located above the first stacked body in the second direction, and
at least one of the plurality of second layers is electrically connected to a second conductor, the second conductor being electrically insulated from the first conductor.

10. The memory device according to claim 9 ,
wherein the first stacked body includes a first region having the semiconductor pillar, a second region in which the first layers and the first conductor are connected to each other, and an insulator which is provided between the first region and the second region,
the first region and the second region are electrically insulated by the insulator.

11. The memory device according to claim 10 ,
wherein the second region is located in the first direction when viewed from the first region.

12. The memory device according to claim 9 ,
wherein the plurality of second layers are electrically connected to respective second conductors each electrically insulated from the first conductor, the respective second conductors being electrically insulated with each other.

13. The memory device according to claim 12 , further comprising:
a plurality of first contact plugs and second contact plugs, each of the first contact plugs being to be connected between one of the plurality of first layers of the first electrode layers and the first conductor, and each of the second contact plugs being to be connected between one of the plurality of second layers of the first electrode layers and one of the respective second conductors.

14. The memory device according to claim 9 ,
wherein the second conductor is provided at a same position as the first conductor in the second direction.

15. The memory device according to claim 9 ,
wherein the first electrode layers function as word lines of a memory cell array and the semiconductor pillar forms memory cells at intersections with the first electrode layers functioning as word lines.

Assignees

• Toshiba Memory Corp

Inventors

• Nojima Kazuhiro
• Shibata Megumi
• Kajino Tomonori
• Shiokawa Taro

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• G11C2029/1202

  Word line control · CPC title

• G11C29/025 Primary

  in signal lines · CPC title