Semiconductor memory device, memory system, and defect detection method

Patent metadata

Field	Value
Publication number	US-11309394-B2
Application number	US-201916562771-A
Country	US
Kind code	B2
Filing date	Sep 6, 2019
Priority date	Feb 13, 2019
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

A semiconductor memory device includes: a first wiring and a second wiring; a first selection transistor, a memory transistor, and a second selection transistor connected between the first wiring and the second wiring; and a third wiring and a fourth wiring connected to gate electrodes of the first selection transistor and the second selection transistor. From a first timing to a second timing, a first voltage that turns the first selection transistor ON is supplied to the third wiring, and a second voltage that turns the second selection transistor OFF is supplied to the fourth wiring. From the second timing to a third timing, a third voltage that turns the first selection transistor OFF is supplied to the third wiring, and at a fourth timing between the first timing and the third timing, at least one of a voltage and a current of the first wiring is detected.

First claim

What is claimed is:

1. A defect detection method for a semiconductor memory device, wherein the semiconductor memory device includes a first wiring and a second wiring, a memory transistor connected between the first wiring and the second wiring, a first selection transistor connected between the first wiring and the memory transistor, a second selection transistor connected between the second wiring and the memory transistor, a third wiring connected to a gate electrode of the first selection transistor, and a fourth wiring connected to a gate electrode of the second selection transistor, the defect detection method comprising:
from a first timing to a second timing, supplying a first voltage that turns the first selection transistor ON to the third wiring, and not supplying a second voltage that turns the first selection transistor OFF to the third wiring;
from the first timing to the second timing, not supplying a third voltage that turns the second selection transistor ON to the fourth wiring, and supplying a fourth voltage that turns the second selection transistor OFF to the fourth wiring;
from the second timing to a third timing, not supplying the first voltage to the third wiring, and supplying the second voltage to the third wiring; and
at a fourth timing between the first timing and the third timing, detecting at least one of a voltage and a current of the first wiring.

2. The defect detection method for the semiconductor memory device according to claim 1 , wherein
the semiconductor memory device includes a fifth wiring connected to a gate electrode of the memory transistor, and
the defect detection method further comprises supplying a potential difference to the first wiring and the fifth wiring at a predetermined timing between the first timing and the second timing.

3. The defect detection method for the semiconductor memory device according to claim 1 , wherein the semiconductor memory device further includes a sense transistor including a gate electrode connected to the first wiring, a latch circuit connected to the sense transistor, a switch transistor connected between the sense transistor and the latch circuit, and a sixth wiring connected to a gate electrode of the switch transistor, and
the defect detection method further comprises supplying a fifth voltage that turns the switch transistor ON to the sixth wiring at the fourth timing.

4. The defect detection method for the semiconductor memory device according to claim 1 , wherein the semiconductor memory device includes a plurality of the memory transistors connected between the first selection transistor and the second selection transistor, and a plurality of fifth wirings connected to respective gate electrodes of the plurality of memory transistors, and
the defect detection method further comprises supplying a sixth voltage to a plurality of the fifth wirings at a predetermined timing between the first timing and the second timing.

5. The defect detection method for the semiconductor memory device according to claim 1 , wherein the semiconductor memory device includes a plurality of the memory transistors connected between the first selection transistor and the second selection transistor, and a plurality of fifth wirings connected to respective gate electrodes of the plurality of memory transistors, and
the defect detection method further comprises:
supplying a seventh voltage to a plurality of the fifth wirings;
repeatedly performing a process that selects one of the fifth wirings from the plurality of fifth wirings, a process that switches a voltage of the selected fifth wiring to an eighth voltage different from the seventh voltage, and a process that detects at least one of a voltage and a current of the first wiring; and

outputting information configured to specify the fifth wiring corresponding to a timing at which the at least one of the voltage and the current of the first wiring detected has changed.

6. The defect detection method for the semiconductor memory device according to claim 1 , wherein the semiconductor memory device includes a plurality of the first wirings, a plurality of the memory transistors connected between the plurality of first wirings and the second wiring, a plurality of first selection transistors connected between the plurality of first wirings and the plurality of memory transistors, and a plurality of second selection transistors connected between the second wiring and the plurality of memory transistors,
the third wiring is commonly connected to gate electrodes of the plurality of first selection transistors,
the fourth wiring is commonly connected to gate electrodes of the plurality of second selection transistors,
the defect detection method further comprises detecting, at the fourth timing, at least one of voltages and currents of the plurality of first wirings, and
the defect detection method further comprises outputting information corresponding to the at least one of the voltages and the currents of the plurality of first wirings detected.

Assignees

• Kioxia Corp

Inventors

• Haraguchi Shinya

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/232 Primary

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H10D30/6891 Primary

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title