Connectivity detection for wafer-to-wafer alignment and bonding

Patent metadata

Field	Value
Publication number	US-11031308-B2
Application number	US-201916426984-A
Country	US
Kind code	B2
Filing date	May 30, 2019
Priority date	May 30, 2019
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad. Connectivity detection circuits test electrical connectivity between the third test pad and the fourth test pad.

First claim

What is claimed is:

1. An apparatus, comprising:
a first workpiece including first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad by a conductive path in the first workpiece;
a second workpiece including second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece, the first and second workpieces bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad; and
connectivity detection circuits in the second workpiece, the connectivity detection circuits configured to test electrical connectivity between the third test pad and the fourth test pad, the connectivity detection circuits include an exclusive OR (XOR) circuit coupled to the fourth test pad and the third test pad to compare the voltage at the fourth test pad with the voltage at the third test pad.

2. The apparatus of claim 1 wherein the connectivity detection circuits are formed of logic components in an active layer in the second workpiece.

3. The apparatus of claim 1 wherein the first workpiece is a first silicon wafer and the second substrate is a second silicon wafer.

4. The apparatus of claim 3 wherein the first silicon wafer includes a plurality of memory dies formed by a first fabrication process and the second silicon wafer includes a plurality of control circuit dies formed by a second fabrication process.

5. The apparatus of claim 1 wherein the XOR circuit is coupled to four or more test pads of the second workpiece to compare voltages at the four or more test pads.

6. The apparatus of claim 1 wherein the conductive path in the first workpiece includes only passive components.

7. The apparatus of claim 1 wherein the first workpiece is an array workpiece that includes a memory array and the second workpiece is a control circuit workpiece that includes control circuits.

8. The apparatus of claim 7 wherein the first active pads are connected to bit lines and word lines in the memory array and the second active pads are connected to read/write circuits and row decoder circuits in the control circuit workpiece.

9. The apparatus of claim 7 wherein the memory array is a 3D non-volatile memory array monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate.

10. The apparatus of claim 1 wherein the first workpiece includes additional test pads in addition to the first and second test pads, the second workpiece includes corresponding additional test pads in addition to the third and fourth test pads, and the connectivity detection circuits are configured to test electrical connectivity of bonds between the additional test pads and the corresponding additional test pads.

11. A method comprising:
aligning a primary surface of an array workpiece that includes a memory array and an opposing primary surface of a control circuit workpiece that includes control circuits;
bonding active pads on the primary surface of the array workpiece with active pads on the primary surface of the control circuit workpiece to electrically couple the memory array and the control circuits;
bonding test pads on the primary surface of the array workpiece with test pads on the primary surface of the control circuit workpiece, the test pads on the primary surface of the array workpiece electrically connected together by one or more conductive paths in the array workpiece; and
subsequently detecting, by connectivity detection circuits located in the control circuit workpiece, electrical connectivity between the test pads on the primary surface of the control circuit workpiece, including performing an exclusive OR (XOR) operation on voltages at the test pads on the primary surface of the control circuit to determine if there is a difference between the voltages at the test pads, to identify misalignment of the test pads on the primary surface of the array workpiece with the test pads on the primary surface of the control circuit workpiece.

12. The method of claim 11 further comprising:
subsequent to detecting the electrical connectivity, determining according to results of detecting the electrical conductivity whether the test pads are aligned;
in response to determining that test pads are aligned, performing additional testing of the array workpiece and the control circuit workpiece; and
in response to determining that test pads are misaligned, discarding the array workpiece and the control circuit workpiece.

13. The method of claim 12 further comprising, in response to determining that the test pads are aligned, subsequently dicing the array workpiece and control circuit workpiece into a plurality of dies, each die including a memory array and control circuits.

14. The method of claim 12 further comprising, in response to determining that the test pads are misaligned, modifying one or more parameters of an alignment and bonding process applied to additional array workpieces and additional control circuit workpieces.

15. The method of claim 11 wherein detecting electrical connectivity between the test pads on the primary surface of the control circuit workpiece to identify misalignment includes determining electrical connectivity by CMOS logic components in an active layer of the control circuit workpiece that form the connectivity detection circuits.

16. The method of claim 15 wherein detecting electrical connectivity between the test pads on the primary surface of the control circuit workpiece includes comparing voltage from one or more test pad on the primary surface of the control circuit workpiece with another voltage from another test pad on the primary surface of the control circuit workpiece or with a reference voltage.

17. The method of claim 11 wherein detecting electrical connectivity between the test pads on the primary surface of the control circuit workpiece to identify misalignment includes performing the XOR operation on four or more voltages at four or more test pads on the primary surface of the control circuit to determine if there is a difference between the four or more voltages at the four or more test pads.

18. A non-volatile storage apparatus, comprising:
a control circuit workpiece that includes control circuits, the control circuit workpiece configured to be wafer-to-wafer bonded to an array workpiece such that the control circuits are electrically coupled to an array of non-volatile memory cells in the array workpiece; and
means for detecting electrical connectivity between pads on the control circuit workpiece and pads on a surface of the array workpiece that are electrically connected together by one or more conductive paths in the array workpiece to identify misalignment between the array workpiece and the control circuit workpiece, the means for detecting electrical connectivity located in the control circuit workpiece, the means for detecting electrical connectivity including an exclusive OR (XOR) circuit coupled to two or more pads on the control circuit workpiece to compare voltages at the two or more pads.

19. The non-volatile storage apparatus of claim 18 wherein the XOR circuit is coupled to four or more pads on the control circuit workpiece to compare voltages at the four or more pads.

Assignees

• Sandisk Technologies Llc

Inventors

• Lee Seungpil
• Kim Kwang-Ho

Classifications

• H10W72/01

  Manufacture or treatment · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/792

  between multiple chips · CPC title