Reducing pattern loading in the etch-back of metal gate

Patent metadata

Field	Value
Publication number	US-12575156-B2
Application number	US-202418731945-A
Country	US
Kind code	B2
Filing date	Jun 3, 2024
Priority date	Jul 16, 2018
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

First claim

What is claimed is:

1 . A method comprising:
forming a first gate dielectric into a first trench between first gate spacers; forming a second gate dielectric extending into a second trench between second gate spacers; depositing a metal layer over the first gate dielectric, wherein the metal layer comprises:
a first portion extending into the first trench; and
a second portion in the second trench;
depositing a filling region into the first trench, wherein in the first trench, the metal layer comprises a first vertical portion and a second vertical portion on opposite sides of the filling region, and wherein at a time before the filling region starts to be deposited into the first trench, an entirety of the second trench has been filled; etching back the first vertical portion and the second vertical portion of the metal layer until first top surfaces of the first vertical portion and the second vertical portion are lower than a second top surface of the filling region; removing an entirety of the filling region in the first trench; and depositing a dielectric material into the first trench.

2 . The method of claim 1 , wherein the dielectric material comprises:
a lower portion in the first trench and between remaining portions of the first vertical portion and the second vertical portion; and an upper portion in the first trench and higher than the remaining portions of the first vertical portion and the second vertical portion.

3 . The method of claim 1 , wherein the first vertical portion and the second vertical portion of the metal layer form portions of a gate electrode, and the method further comprises:
forming a gate contact plug at least partially in the first trench.

4 . The method of claim 3 , wherein a part of the gate contact plug is lower than top surfaces of the first vertical portion and the second vertical portion.

5 . The method of claim 1 , wherein the depositing the filling region comprises depositing an additional dielectric material.

6 . The method of claim 1 , wherein the depositing the metal layer comprises depositing a work-function layer.

7 . The method of claim 6 , wherein the depositing the metal layer further comprises depositing a filling-metal layer comprising tungsten or cobalt over the work-function layer.

8 . The method of claim 1 further comprising, after the dielectric material is deposited into the first trench, performing a planarization process on the dielectric material.

9 . The method of claim 1 , wherein the first trench is lower than top surfaces of the first gate spacers.

10 . The method of claim 1 , wherein the depositing the filling region comprises depositing amorphous silicon or polysilicon.

11 . The method of claim 10 , wherein the depositing the filling region comprises depositing the amorphous silicon.

12 . The method of claim 1 , wherein in a cross-section of the first trench, the dielectric material is filled into a U-shaped basin formed of the metal layer.

13 . A method comprising:
forming a gate dielectric extending into a trench, wherein the trench is between opposite gate spacers; depositing a conductive layer over the gate dielectric; depositing a filling region on the conductive layer; performing a planarization process to remove excess portions of the filling region, the conductive layer, and the gate dielectric; etching back the conductive layer, so that the filling region comprises a portion higher than remaining portions of the conductive layer; etching the filling region to remove an entirety of the filling region; after the filling region is etched, forming a dielectric hard mask in the trench; performing an etching process to etch the dielectric hard mask and to form a contact opening; and forming a gate contact plug in the contact opening.

14 . The method of claim 13 , wherein the depositing the filling region comprises depositing a non-dielectric material.

15 . The method of claim 14 , wherein the depositing the filling region comprises depositing amorphous silicon or polysilicon.

16 . The method of claim 13 , wherein after the conductive layer is etched back, the conductive layer comprises a bottom portion under the filling region, and vertical portions on sidewalls of the filling region.

17 . The method of claim 13 , wherein when the conductive layer is etched back, the gate dielectric is simultaneously etched.

18 . A method comprising:
forming an opening between gate spacers, wherein a semiconductor region is exposed through the opening; forming a gate dielectric and a gate electrode in the opening; forming a filling region filling the opening; planarizing the filling region, the gate dielectric, and the gate electrode, so that top surfaces of the gate spacers are revealed; etching the gate dielectric and the gate electrode; after the gate dielectric and the gate electrode are etched, removing the filling region, wherein the removing the filling region results in a top surface and sidewalls of the gate electrode to be exposed; forming a hard mask filling the opening and over the gate electrode, wherein the hard mask is filled into a space left by the filling region that is removed after the gate dielectric and the gate electrode are etched; and forming a gate contact plug in the hard mask, wherein the gate contact plug is electrically connected to the gate electrode, and wherein after the hard mask and the gate contact plug are formed, the gate contact plug is in contact with the top surface and the sidewalls of the gate electrode.

19 . The method of claim 18 , wherein the etching the gate dielectric and the gate electrode is performed using a chlorine-based etching gas.

20 . The method of claim 18 , wherein a portion of the gate contact plug is formed in the space left by the filling region that is removed after the gate dielectric and the gate electrode are etched.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Po-Chin
• Wu wei-hao
• Lin Li-Te
• Lin Pinyen

Classifications

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title