Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10121675-B2
Application number	US-201715649909-A
Country	US
Kind code	B2
Filing date	Jul 14, 2017
Priority date	Dec 29, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (ESL) covering the source/drain epitaxial layers. An opening is formed in the ILD layer by etching. A dielectric filling layer is formed in the opening. By using wet etching, the ILD layer disposed above the source/drain epitaxial layers is removed. The ESL disposed on the source/drain epitaxial layers is removed, thereby at least partially exposing the source/drain epitaxial layers. A conductive material is formed over the exposed source/drain epitaxial layers.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate;
source/drain epitaxial layers disposed between two adjacent gate structures; and
an etching-stop layer (ESL) covering the source/drain epitaxial layers;

forming an opening in the ILD layer by etching;
forming a dielectric filling layer in the opening;
removing, by using wet etching, the ILD layer disposed above the source/drain epitaxial layers;
removing the ESL disposed on the source/drain epitaxial layers, thereby at least partially exposing the source/drain epitaxial layers; and
forming a conductive material over the exposed source/drain epitaxial layers.

2. The method of claim 1 , wherein dielectric materials for the ESL, the cap insulating layer and the dielectric filling layer are different from a dielectric material for the ILD layer.

3. The method of claim 2 , wherein the dielectric material for the ESL is same as the dielectric material for the dielectric filling layer.

4. The method of claim 1 , wherein:
the ESL is made of at least one selected from the group consisting of SiN and SiCN,
the cap insulating layer is made of at least one selected from the group consisting of SiN and SiON,
the dielectric filling layer is made of at least one selected from the group consisting of SiN and SiCN, and
the ILD layer is made of SiO 2 .

5. The method of claim 4 , wherein:
each of the gate structures further includes sidewalls spacers formed on opposing sides of the metal gate, and
the sidewall spacers are made of at least one selected from the group consisting of SiCN and SiOCN.

6. The method of claim 1 , wherein the wet etching utilizes dilute HF.

7. The method of claim 1 , wherein in forming the opening, the cap insulating layer is partially removed and the dielectric filling layer is formed on a portion of the cap insulating layer where the cap insulating layer is partially removed.

8. The method of claim 7 , wherein:
each of the gate structures further includes sidewalls spacers formed on opposing sides of the metal gate, and
in forming the opening, the ESL and the sidewall spacers are partially removed and the dielectric filling layer is formed in contact with the sidewall spacers.

9. The method of claim 1 , wherein the opening is formed by dry etching using a hard mask pattern including a TiN layer.

10. The method of claim 1 , wherein:
after the opening is formed, part of the ILD layer remains under the opening, and
the dielectric filling layer is formed in the opening above the remaining ILD layer.

11. A method of manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
first to fourth gate structures, each having a metal gate, sidewall spacers disposed on opposing sides of the metal gate and a cap insulating layer disposed over the metal gate, the first to fourth gate structures being arranged in this order along a first direction;
a first source/drain (S/D) epitaxial layer and a second S/D epitaxial layer, both disposed between the second gate structure and the third gate structure; and
an etching-stop layer (ESL) covering the first and second S/D epitaxial layers;

forming a first opening in the ILD layer by etching over an area including a region between the first and second S/D epitaxial layer;
forming a dielectric filling layer in the first opening;
removing, by using wet etching, the ILD layer disposed above the first and second S/D epitaxial layers, thereby forming a second opening and a third opening, respectively, and the ILD layer disposed between the first gate structure and the second gate structure, thereby forming a fourth opening;
removing the ESL disposed on the first and second S/D epitaxial layers, thereby at least partially exposing the first and second S/D epitaxial layers; and
forming a conductive material over the exposed first and second S/D epitaxial layers, thereby forming a first S/D contact on the first S/D epitaxial layer and a second S/D contact on the second S/D epitaxial layer, and in the fourth opening, thereby forming a contact bar.

12. The method of claim 11 , wherein dielectric materials for the ESL, the cap insulating layer, the sidewall spacers and the dielectric filling layer are different from a dielectric material for the ILD layer.

13. The method of claim 11 , wherein:
the ESL is made of at least one selected from the group consisting of SiN and SiCN,
the cap insulating layer is made of at least one selected from the group consisting of SiN and SiON,
the sidewall spacers are made of at least one selected from the group consisting of SiCN and SiOCN,
the dielectric filling layer is made of at least one selected from the group consisting of SiN and SiCN, and
the ILD layer is made of SiO 2 .

14. The method of claim 11 , wherein the wet etching utilizes dilute HF.

15. The method of claim 11 , wherein in forming the first opening, the cap insulating layer is partially removed and the dielectric filling layer is formed on a removed portion of the cap insulating layer.

16. The method of claim 15 , wherein, in forming the first opening, the ESL and the sidewall spacers of the second and third gate structures are partially removed and the dielectric filling layer is formed in contact with the sidewall spacers of the second and third gate structures.

17. The method of claim 11 , wherein the first opening is formed by dry etching using a hard mask pattern including a TiN layer.

18. The method of claim 11 , wherein:
after the first opening is formed, part of the ILD layer remains under the first opening, and
the dielectric filling layer is formed in the first opening above the remaining ILD layer.

19. A method of manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
a first gate structure and a second gate structure, each of which includes a metal gate and a cap insulating layer disposed over the metal gate;
source/drain epitaxial layers disposed between the first and second gate structures; and
an etching-stop layer (ESL) covering the source/drain epitaxial layers;

forming openings in the ILD layer by etching, the openings partially overlapping source/drain epitaxial layers, in plan view;
forming a dielectric filling layer in the openings;
removing, by using wet etching, the ILD layer disposed above the source/drain epitaxial layers;
removing the ESL disposed on the source/drain epitaxial layers, thereby at least partially exposing the source/drain epitaxial layers; and
forming a conductive material over the exposed source/drain epitaxial layers.

20. The method of claim 19 , wherein one of the openings partially overlaps two of the source/drain epitaxial layers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Chen-Ming
• Yang Fu-Kai
• Wang Mei-Yun

Classifications

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10P50/283 Primary

  by chemical means · CPC title