Forming sidewall spacers using isotropic etch

Patent metadata

Field	Value
Publication number	US-9852947-B1
Application number	US-201615271318-A
Country	US
Kind code	B1
Filing date	Sep 21, 2016
Priority date	Sep 21, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A method includes etching a dielectric layer to form an opening, with a component of a transistor being exposed through the opening. A spacer layer is formed, and includes a horizontal portion at a bottom of the opening, and a vertical portion in the opening. The vertical portion is on a sidewall of the dielectric layer. An isotropic etch is performed on the spacer layer to remove the horizontal portion, and the vertical portion remains after the isotropic etch. The remaining vertical portion forms a contact plug spacer. A conductive material is filled into the opening to form a contact plug.

First claim

What is claimed is:

1. A method comprising:
etching a dielectric layer to form an opening, wherein a component of a transistor is exposed through the opening;
forming a spacer layer comprising:
a horizontal portion at a bottom of the opening; and
a vertical portion in the opening, wherein the vertical portion is on a sidewall of the dielectric layer;

performing an isotropic etch on the spacer layer to remove the horizontal portion, and the vertical portion remains after the isotropic etch, and the remaining vertical portion forms a contact plug spacer; and
filling a conductive material into the opening to form a contact plug.

2. The method of claim 1 , wherein the forming the spacer layer comprises:
depositing a sub-layer of the spacer layer; and
bombarding the sub-layer to loosen the sub-layer.

3. The method of claim 2 , wherein during the bombarding, materials of the horizontal portion are loosened and remain at the bottom of the opening.

4. The method of claim 2 , wherein the forming the spacer layer is performed using atomic layer deposition, and the bombarding is performed after each atomic layer of the spacer layer is formed.

5. The method of claim 1 , wherein in the isotropic etch, the horizontal portion has a higher etching rate than the vertical portion.

6. The method of claim 1 , wherein the component of the transistor comprises a source/drain region, a source/drain silicide region, or a gate electrode.

7. The method of claim 1 , wherein the forming the spacer layer comprises forming a silicon nitride layer.

8. A method comprising:
etching a dielectric layer to form an opening, wherein a component of a transistor is exposed through the opening;
forming a spacer layer comprising a plurality of cycles, and each of the cycles comprises:
depositing a sub-layer of the spacer layer; and
bombarding the sub-layer to loosen a horizontal portion of the sub-layer, wherein the horizontal portion is at a bottom of the opening;

removing the horizontal portions of the sub-layers formed by the plurality of cycles; and
filling a conductive material into the opening to form a contact plug, wherein a vertical portion of the spacer layer encircles the contact plug.

9. The method of claim 8 , wherein during the bombarding, materials of the horizontal portion are loosened and remain at the bottom of the opening.

10. The method of claim 8 , wherein the forming the spacer layer is performed using atomic layer deposition, and the bombarding is performed after each atomic layer of the spacer layer is formed.

11. The method of claim 8 , wherein the component of the transistor comprises a source/drain region or a source/drain silicide region.

12. The method of claim 8 , wherein the horizontal portions of the sub-layers formed by the plurality of cycles are removed in an isotropic etch, and in the isotropic etch, the horizontal portions has a higher etching rate than the vertical portions.

13. The method of claim 8 , wherein the horizontal portions of the sub-layers formed by the plurality of cycles are removed in an isotropic etch, and the isotropic etch comprises a dry etch.

14. The method of claim 8 , wherein the horizontal portions of the sub-layers formed by the plurality of cycles are removed in an isotropic etch, and the isotropic etch comprises a wet etch.

15. The method of claim 8 , wherein the depositing the sub-layer is performed using radicals of nitrogen, and the bombarding is performed using ions of nitrogen.

16. A method comprising:
forming an Inter-Layer Dielectric (ILD) to cover a gate stack;
etching the ILD to form a source/drain contact opening;
implanting a semiconductor substrate through the source/drain contact opening to form a source/drain region;
forming a blanket spacer layer to extend into the source/drain contact opening;
performing an isotropic etch on the blanket spacer layer to remove a portion of the blanket spacer layer in the source/drain contact opening, and a remaining portion of the blanket spacer layer in the source/drain contact opening forms a contact plug spacer; and
filling a conductive material into the source/drain contact opening to form a source/drain contact plug, wherein the source/drain contact plug is encircled by the contact plug spacer.

17. The method of claim 16 further comprising:
etching the ILD to form a gate contact opening, wherein the blanket spacer layer is formed before the gate contact opening is formed, and an additional portion of the conductive material is filled into the gate contact opening to form a gate contact plug, and the gate contact plug is in physical contact with the ILD.

18. The method of claim 16 further comprising:
etching the ILD to form a gate contact opening, wherein the blanket spacer layer extends into both the gate contact opening and the source/drain contact opening.

19. The method of claim 16 , wherein immediately after the blanket spacer layer is formed, horizontal portions of the blanket spacer layer have a lower density than vertical portions of the blanket spacer layer.

20. The method of claim 16 , wherein in the isotropic etch, horizontal portions of the blanket spacer layer have a higher etching rate than vertical portions of the blanket spacer layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ko Chung-Ting
• Hsu Kuang-Yuan

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10W20/095

  by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096) · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title