Methods of forming replacement gate structures for semiconductor devices and the resulting devices

Patent metadata

Field	Value
Publication number	US-2016163601-A1
Application number	US-201414560102-A
Country	US
Kind code	A1
Filing date	Dec 4, 2014
Priority date	Dec 4, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities.

First claim

What is claimed:

1 . A method of forming replacement gate structures above a substrate, the method comprising:
forming first and second replacement gate cavities above said substrate; forming a high-k gate insulation layer in said first and second replacement gate cavities; forming a work-function adjusting metal layer in said first and second replacement gate cavities above said high-k gate insulation layer; forming a metal protection layer above said work-function adjusting layer in said first and second replacement gate cavities, said metal protection layer being formed so as to pinch-off said first replacement gate cavity while leaving said second replacement gate cavity partially un-filled; forming a first bulk conductive metal layer such that it is positioned within said un-filled portion of said second replacement gate cavity above said metal protection layer while said first replacement gate cavity is substantially free of said first bulk conductive metal layer; after forming said first bulk conductive metal layer, performing at least one etching process to selectively remove substantially all of said metal protection layer in said first replacement gate cavity while leaving a portion of said metal protection layer in said second replacement gate cavity; forming a second bulk conductive metal layer within said first and second replacement gate cavities; performing at least one recess etching process to recess said second bulk conductive metal layer within said first replacement gate cavity and to recess said second bulk conductive metal layer and said first bulk metal conductive layer within said second replacement gate cavity so as to define first and second gate-cap cavities in said first and second replacement gate cavities, respectively; and forming gate cap layers within said first and second gate-cap cavities.

2 . The method of claim 1 , wherein said forming said high-k gate insulation layer comprises forming a layer of hafnium oxide.

3 . The method of claim 1 , wherein said forming said first and second bulk conductive material layers comprises forming said first and second bulk conductive material layers of the same conductive material.

4 . The method of claim 1 , wherein said forming said first and second replacement gate cavities comprises forming said first and second replacement gate cavities such that said first and second replacement gate cavities have different lateral dimensions.

5 . The method of claim 1 , wherein said forming said first and second replacement gate cavities comprises forming said first replacement gate cavity for a transistor having a gate length less than 40 nm and forming said second replacement gate cavity for a transistor having a gate length greater than 40 nm.

6 . The method of claim 1 , wherein said performing said at least one etching process to selectively remove substantially all of said metal protection layer in said first replacement gate cavity while leaving a portion of said metal protection layer in said second replacement gate cavity comprises:
performing at least one first recess etching process to remove portions of a sidewall spacer and portions of said high-k gate insulation layer positioned within or adjacent said first and second replacement gate cavities; performing at least one second recess etching process to selectively remove portions of said work-function adjusting metal layer selectively relative to at least said high-k gate insulation layer and said metal protection layer within said first and second replacement gate cavities; and performing at least one third recess etching process to selectively remove substantially all of said metal protection layer in said first replacement gate cavity while leaving a portion of said metal protection layer in said second replacement gate cavity.

7 . A method of forming replacement gate structures above a substrate, the method comprising:
forming first and second replacement gate cavities above said substrate for first and second transistor devices, respectively, said first transistor device having a channel length of less than 40 nm, said second transistor device having a channel length that is greater than 40 nm; forming a high-k gate insulation layer in said first and second replacement gate cavities; forming a work-function adjusting metal layer in said first and second replacement gate cavities above said high-k gate insulation layer; forming a metal protection layer above said work-function adjusting layer in said first and second replacement gate cavities, said metal protection layer being formed so as to pinch-off said first replacement gate cavity while leaving said second replacement gate cavity partially un-filled; forming a first bulk conductive metal layer such that it is positioned within said un-filled portion of said second replacement gate cavity above said metal protection layer while said first replacement gate cavity is substantially free of said first bulk conductive metal layer; performing at least one first recess etching process to remove portions of a sidewall spacer and portions of said high-k gate insulation layer positioned within or adjacent said first and second replacement gate cavities; performing at least one second recess etching process to selectively remove portions of said work-function adjusting metal layer selectively relative to at least said high-k gate insulation layer and said metal protection layer within said first and second replacement gate cavities; performing at least one third recess etching process to selectively remove substantially all of said metal protection layer in said first replacement gate cavity while leaving a portion of said metal protection layer in said second replacement gate cavity; forming a second bulk conductive metal layer within said first and second replacement gate cavities; performing at least one recess etching process to recess said second bulk conductive metal layer within said first replacement gate cavity and to recess said second bulk conductive metal layer and said first bulk metal conductive layer within said second replacement gate cavity so as to define first and second gate-cap cavities in said first and second replacement gate cavities, respectively; and forming gate cap layers within said first and second gate-cap cavities.

8 . A method of forming a replacement gate structure above a substrate, the method comprising:
forming a replacement gate cavity above said substrate; forming a high-k gate insulation layer in said replacement gate cavity; forming a work-function adjusting metal layer in said replacement gate cavity above said high-k gate insulation layer; forming a sacrificial metal protection layer above said work-function adjusting layer in said replacement gate cavity, said sacrificial metal protection layer being formed so as to pinch-off said replacement gate cavity; performing at least one etching process to selectively remove substantially all of said sacrificial metal protection layer in said replacement gate cavity; after selectively removing substantially all of said sacrificial metal protection layer from said replacement gate cavity, forming a bulk conductive metal layer within said replacement gate cavity; performing at least one recess etching process to recess said bulk conductive metal layer within said replacement gate cavity so as to define a gate-cap cavity within said replacement gate cavity; and forming a gate cap layer within said replacement gate cavity.

9 . The method of claim 8 , wherein said forming said high-k gate insulation layer comprises forming a layer of hafnium oxide.

10 . The method of claim 8 , wherein said forming said replacement ga

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Park Chanro
• Lin Sean Xuan

Classifications

• H10P50/264

  by chemical means · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title