Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017194210-A1
Application number	US-201615292157-A
Country	US
Kind code	A1
Filing date	Oct 13, 2016
Priority date	Dec 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A semiconductor device including a substrate including a first and second region; a first active region formed in an upper portion of the substrate in the first region; a second active region formed in an upper portion of the substrate in the second region; a first gate structure extending across the first active region, having a first gate length, and including a first high-k dielectric layer, a first lower metal layer, and a first upper metal layer; a second gate structure extending across the second active region, having a second gate length, and including a second high-k dielectric layer, a second lower metal layer having at least one metal layer, and a second upper metal layer; and spacers at sides of each of the first and second gate structures, a cross section of each of the first and second high-k dielectric layers has a U-shape, a cross section of each of the first and second lower metal layers has a U-shape, the first and second lower metal layers covering bottom surfaces and inner side surfaces of the corresponding first and second high-k dielectric layers, respectively, the first high-k dielectric and first lower metal layer are buried under the first upper metal layer, and the second high-k dielectric and second lower metal layer are buried under the second upper metal layer.

First claim

1 - 14 . (canceled)

15 . A method of manufacturing a semiconductor device, the method comprising:
forming a dummy gate structure extending in one direction on a substrate; forming spacers at both sidewalls of the dummy gate structure; forming an interlayer insulating layer covering the substrate and a result on the substrate, and planarizing the interlayer insulating layer to expose an upper surface of the dummy gate structure; removing the dummy gate structure, and sequentially forming a high-k dielectric layer, at least one metal layer, and a sacrificial layer on a portion in which the dummy gate structure is removed and on the interlayer insulating layer; leaving a portion of the sacrificial layer between the spacers by etching the sacrificial layer through ultraviolet (UV) irradiation, and exposing the at least one metal layer on side surfaces of the spacers and on the interlayer insulating layer; etching and removing portions of the exposed at least one metal layer and the high-k dielectric layer except for the portions covered by the sacrificial layer; removing the sacrificial layer, and forming a lower metal layer having the at least one metal layer, of which a cross section is buried as a U-shaped structure; and forming an upper metal layer on the lower metal layer and forming a gate structure.

16 . The method as claimed in claim 15 , wherein:
a first region and a second region are defined on the substrate; forming the dummy gate structure includes: forming a first dummy gate structure in the first region and having a first gate length defined as a distance between a source and a drain, and forming a second dummy gate structure in the second region and having a second gate length which is at least two times the first gate length; forming the lower metal layer includes forming a first lower metal layer in the first region and forming a second lower metal layer in the second region; and forming the gate structure includes: forming a first gate structure in the first region and having the first gate length by forming a first upper metal layer on the first lower metal layer, and forming a second gate structure in the second region and having the second gate length by forming a second upper metal layer on the second lower metal layer.

17 . The method as claimed in claim 16 , wherein:
a thickness of the sacrificial layer that is removed through the UV irradiation in the first region is substantially identical to a thickness of the sacrificial layer that is removed through the UV irradiation in the second region; and heights of protruding portions at both side surfaces of the second lower metal layer from an upper surface of the substrate are less than or equal to heights of protruding portions at both side surfaces of the first lower metal layer therefrom.

18 . The method as claimed in claim 15 , wherein, after the etching of the sacrificial layer through the UV irradiation, the at least one metal layer is maintained to have an identical thickness and profile before the etching of the sacrificial layer.

19 . The method as claimed in claim 15 , wherein the at least one metal layer is formed to have any type of a first type including a TaN layer, a second type including a TaN layer and a TiN layer, and a third type including a first TiN layer, a TaN layer, and a second TiN layer.

20 . The method as claimed in claim 15 , wherein:
the upper metal layer is formed of TiN; and forming the gate structure includes planarizing the upper metal layer after coating the upper metal layer.

21 . The method as claimed in claim 15 , wherein the sacrificial layer is formed of a spin on hardmask.

22 . The method as claimed in claim 15 , wherein the sacrificial layer is formed at a temperature in a range of 150° C. to 300° C.

23 . The method as claimed in claim 15 , wherein the UV irradiation includes performing a baking process at a temperature in a range of 150° C. to 300° C. with power in a range of 1 W to 1,000 W.

24 . The method as claimed in claim 15 , further comprising, prior to forming the dummy gate structure, forming a trench by etching the substrate, forming a device isolation layer by filling a lower portion of the trench with an insulating material, and forming at least one fin protruding from the device isolation layer and extending in a first direction,
wherein the dummy gate structure has a structure extending in a second direction perpendicular to the first direction and covering a portion of the fin.

25 . A method of manufacturing a semiconductor device, the method comprising:
forming a trench by etching a substrate, forming a device isolation layer by filling a lower portion of the trench with an insulating material, and forming at least one fin protruding from the device isolation layer and extending in a first direction; forming a dummy gate structure extending in a second direction perpendicular to the first direction, covering a portion of the fin, and having a gate length defined as a distance between a source and a drain; forming spacers that extend in the second direction and that cover the portion of the fin on both side surfaces of the dummy gate structure; forming an interlayer insulating layer that covers the substrate and a result on the substrate, and planarizing the interlayer insulating layer to expose an upper surface of the dummy gate structure; removing the dummy gate structure, and sequentially forming a high-k dielectric layer, at least one metal layer, and a sacrificial layer on a portion in which the dummy gate structure is removed and on the interlayer insulating layer; leaving a portion of the sacrificial layer between the spacers by etching the sacrificial layer through ultraviolet (UV) irradiation, and exposing the at least one metal layer on side surfaces of the spacers and on the interlayer insulating layer; etching and removing portions of the exposed at least one metal layer and the high-k dielectric layer except for the portions covered by the sacrificial layer; removing the sacrificial layer, and forming a lower metal layer having the at least one metal layer, of which a cross section is buried as a U-shaped structure; and forming an upper metal layer on the lower metal layer and forming a gate structure.

26 . The method as claimed in claim 25 , wherein:
a first region and a second region are defined on the substrate; forming the dummy gate structure includes: forming a first dummy gate structure in the first region and having a first gate length, and forming a second dummy gate structure in the second region and having a second gate length that is at least two times the first gate length; forming the lower metal layer includes: forming a first lower metal layer in the first region, and forming a second lower metal layer in the second region; and forming the gate structure includes: forming a first gate structure in the first region and having the first gate length by forming a first upper metal layer on the first lower metal layer, and forming a second gate structure in the second region and having the second gate length by forming a second upper metal layer on the second lower metal layer.

27 . The method as claimed in claim 26 , wherein:
a thickness of the sacrificial layer that is removed through the UV irradiation in the first region is substantially identical to a thickness of the sacrificial layer that is removed through the UV irradiation in the second region; and heights of protruding portions at both side surfaces of the second lower metal layer from an upper surface of the fin are less than or equal to heights of protruding p

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh Tae-Hwan
• Yoon Kwang-Sub
• Jeong Yong-Chul
• Oh Seung-Ho
• Choi Ji-Young
• Lee Suk-Won
• Shin Woo-Jeong
• Jung Myoung-Ki
• Kim Min-Jung

Classifications

• H10P14/6902

  composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon · CPC title

• H10P14/683

  carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P14/6342

  Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title

• H10P14/68

  Organic materials, e.g. photoresists · CPC title