Methods of testing nonvolatile memory devices and nonvolatile memory devices

Patent metadata

Field	Value
Publication number	US-12573449-B2
Application number	US-202318341815-A
Country	US
Kind code	B2
Filing date	Jun 27, 2023
Priority date	Oct 18, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

In a method of testing a nonvolatile memory device including a first semiconductor layer in which and a second semiconductor layer formed prior to the first semiconductor layer, circuit elements including a page buffer circuit and at least one driver spaced apart from the page buffer circuit are provided in the second semiconductor layer, an on-state of nonvolatile memory cells which are not connected to the page buffer circuit is mimicked by providing at least one discharging path between a sensing node and a plurality of discharge transistors of the at least one driver, a sensing and latching operation with the on-state being mimicked is performed in the page buffer circuit and whether the page buffer circuit operates normally is determined based on a result of the sensing and latching operation.

First claim

What is claimed is:

1 . A method of fabricating a nonvolatile memory device that includes a first semiconductor layer and a second semiconductor layer, wherein a plurality of nonvolatile memory cells, a plurality of word-lines, and a plurality of bit-lines are provided on the first semiconductor layer and the second semiconductor layer is formed prior to the first semiconductor layer, the method comprising:
providing circuit elements including a page buffer circuit and at least one driver that are on the second semiconductor layer by forming semiconductor elements on the second semiconductor layer and forming patterns for wiring the semiconductor elements on the second semiconductor layer, the at least one driver spaced apart from the page buffer circuit; mimicking an on-state of nonvolatile memory cells which are not connected to the page buffer circuit by providing at least one discharging path between a sensing node of the page buffer circuit and a plurality of discharge transistors of the at least one driver, wherein the at least one driver is connected to a connection transistor coupled to a bit-line node of the page buffer circuit through a conduction line; performing, in the page buffer circuit, a sensing and latching operation with the on-state being mimicked; and determining whether the page buffer circuit operates normally based on a result of the sensing and latching operation, wherein at least two of the plurality of discharge transistors are commonly connected to a connection node and to a ground node as commonly connected discharge transistors, the providing the at least one discharging path includes turning on the at least two commonly connected discharge transistors with a common gate voltage, and the method includes determining a number of the plurality of discharge transistors to turn on, the number of the plurality of discharge transistors to turn on being inversely related to a time interval of discharge.

2 . The method of claim 1 , wherein mimicking the on-state of nonvolatile memory cells includes:
pre-charging the sensing node to a level of a power supply voltage; interrupting a current supply to the sensing node; and turning on at least one of the plurality of discharge transistors, and wherein performing the sensing and latching operation includes: latching a voltage level of the sensing node.

3 . The method of claim 2 , wherein the plurality of discharge transistors include k discharge transistors coupled in parallel between the connection node and the ground node,
wherein k is a natural number greater than two and the connection node is connected to the conduction line, and the turning on the at least one of the plurality of discharge transistors includes turning on j discharge transistors of the k discharge transistors, j being a natural number less than or equal to k and greater than or equal to one.

4 . The method of claim 2 , wherein the plurality of discharge transistors include k discharge transistors coupled in parallel between a connection node and the ground node,
wherein k is a natural number greater than two and the connection node is connected to the conduction line, and the turning on the at least one of the plurality of discharge transistors includes turning on the k discharge transistors.

5 . The method of claim 1 , wherein the at least one driver includes:
a first driver including a plurality of first discharge transistors, the first driver connected to a first connection transistor through a first conduction line, the first connection transistor coupled to a first bit-line node connected to a first sensing node of the page buffer circuit; and a second driver including a plurality of second discharge transistors, the second driver connected to a second connection transistor through a second conduction line, the second connection transistor coupled to a second bit-line node connected to a second sensing node of the page buffer circuit.

6 . The method of claim 5 , wherein the mimicking the on-state of nonvolatile memory cells includes:
pre-charging the first sensing node to a level of a power supply voltage and pre-charging the second sensing node to the level of the power supply voltage; interrupting a current supply to each of the first sensing node and the second sensing node; and during a first time interval, turning on at least one of the plurality of first discharge transistors and at least one of the plurality of second discharge transistors.

7 . The method of claim 6 , wherein the performing the sensing and latching operation includes latching a voltage level of each of the first sensing node and the second sensing node.

8 . The method of claim 6 , wherein
each of the plurality of first discharge transistors and the plurality of second discharge transistors include k discharge transistors, k being a natural number greater than two, and the turning on at least one of the plurality of first discharge transistors and at least one of the plurality of second discharge transistors includes: turning on j discharge transistors of the first k discharge transistors, j being a natural number less than or equal to k and greater than or equal to one; and turning on i discharge transistors of second k discharge transistors, i being a natural number less than or equal to than k and greater than or equal to j.

9 . The method of claim 5 , wherein the mimicking the on-state of nonvolatile memory cells includes:
pre-charging the first sensing node to a level of a power supply voltage and the second sensing node to the level of the power supply voltage; interrupting a current supply to each of the first sensing node and the second sensing node; and turning on at least one of the plurality of second discharge transistors during a first time interval while turning off the plurality of first discharge transistors during the first time interval.

10 . The method of claim 9 , wherein the performing the sensing and latching operation includes latching a voltage level of each of the first sensing node and the second sensing node.

11 . The method of claim 9 ,
wherein each of the plurality of first discharge transistors and the plurality of second discharge transistors include k discharge transistors, k being a natural number greater than two, the turning on at least one of the plurality of second discharge transistors and at least one of the plurality of second discharge transistors includes: turning on j discharge transistors of the second k discharge transistors, j being a natural number less than or equal to k and greater than or equal to one.

12 . The method of claim 1 , wherein the page buffer circuit includes:
a plurality of page buffers arranged in a first horizontal direction; and a plurality of cache latches spaced apart from the plurality of page buffers in the first horizontal direction, the plurality of cache latches respectively corresponding to the plurality of page buffers and being commonly connected to a combined sensing node, wherein each of the plurality of page buffers includes: a pass transistor connected to each sensing node and configured to be driven in response to a pass control signal, and a bit-line selection transistor coupled to the bit-line node and having a gate configured to receive a bit-line selection signal; a first n-channel metal-oxide semiconductor (NMOS) transistor which is coupled between the bit-line selection transistor and an internal node and has a gate configured to receive a bit-line shut-off signal; a second NMOS transistor which is coupled between the sensing node and the internal node and has a gate configured to receive a bit-line co

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Yeonwook
• Lee Myeongwoo
• Park Jongchul

Classifications

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C29/025

  in signal lines · CPC title

• G11C16/24

  Bit-line control circuits · CPC title