Memory device performing test on memory cell array and method of operating the same

Patent metadata

Field	Value
Publication number	US-10510429-B2
Application number	US-201816007528-A
Country	US
Kind code	B2
Filing date	Jun 13, 2018
Priority date	Oct 27, 2017
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.

First claim

What is claimed is:

1. A memory device, comprising:
a memory cell array connected to a bit line, first word lines, and second word lines, the memory cell array including a first memory cell and second memory cells, the first memory cell being connected between one of the first word lines and the bit line, and the second memory cells being connected between a respective one of the second word lines and the bit line;
a first word line driver configured to drive the first word lines;
a second word line driver configured to drive the second word lines; and
a test manager configured to,
control the second word line driver in a test mode to drive N second word lines of the second word lines to change a capacitance of the bit line by connecting a cell capacitor included in each of the second memory cells associated with the N second word lines to the bit line connected to the first memory cell such that the capacitance of the bit line connected to the first memory cell increases, N being an integer greater than or equal to one, and
control, after the capacitance of the bit line connected to the first memory cell is changed, the first word line driver such that the first word lines are driven to test the first word lines.

2. The memory device of claim 1 , wherein
the memory device is configured to test the first memory cell, and to not to test the second memory cells.

3. The memory device of claim 1 , wherein the second word lines comprise:
dummy word lines that are not used for writing data to the memory cell array.

4. The memory device of claim 3 , wherein
the second word lines include X first dummy word lines and Y second dummy word lines, X and Y being integers greater than or equal to one, and
the second word line driver includes,
a first dummy word line driver configured to drive the X first dummy word lines; and
a second dummy word line driver configured to drive the Y second dummy word lines.

5. The memory device of claim 4 , wherein X and Y are different integers.

6. The memory device of claim 1 , wherein
the second word lines include normal word lines connected to the first memory cell, and
the first memory cell is one of a normal memory cell and a repair memory cell, the normal memory cell being a cell to which data is written, and the repair memory cell being a cell configured to replace the normal memory cell.

7. The memory device of claim 6 , further comprising:
a logic gate connected to the normal word lines, the logic gate configured to switch which one of the first word line driver and the second word line driver drive the normal word lines.

8. The memory device of claim 7 , wherein
the logic gate is an OR gate configured to drive the normal word lines, when a word line drive signal is received from the first word line driver or the second word line driver.

9. The memory device of claim 6 , wherein
the normal word lines included in the second word lines include one of first normal word lines and second normal word lines, the first normal word lines being in a first area having ‘0’ as a most significant bit (MSB), and the second normal word lines being in a second area having ‘1’ as the MSB, and
the test manager is configured to,
control driving of the second normal word lines, when the first word lines are in the first area, and
control driving of the first normal word lines, when the first word lines are in the second area.

10. The memory device of claim 1 , further comprising:
a test mode register set configured to output a test signal, when the memory device enters the test mode based on a test mode command.

11. The memory device of claim 1 , wherein the test manager is configured to adjust the capacitance of the bit line by adjusting a voltage level of a word line driving voltage applied to the second word lines.

12. The memory device of claim 11 , wherein the voltage level of the word line driving voltage is proportional to the capacitance of the bit line.

13. The memory device of claim 1 , wherein the memory device is a dynamic random access memory (DRAM).

14. A volatile memory device, comprising:
a memory cell array including a bit line and a plurality of word lines, the bit line simultaneously connected to a first memory cell to be tested and a plurality of second memory cells that are not to be tested, the plurality of word lines connected to respective ones of the plurality of second memory cells, the first memory cell including a first cell capacitor and the plurality of second memory cells each including a second cell capacitor;
a word line driver configured to drive N word lines of the plurality of word lines connected to the respective ones of the plurality of second memory cells in response to a word line enable signal, N being an integer greater than or equal to one; and
a test manager configured to,
receive a test mode command including capacitance information,
outputting the word line enable signal to the word line driver to drive the N word lines of the plurality of word lines based on the test mode command,
control a connection between the second cell capacitor included in each of the plurality of second memory cell associated with the N second word lines.

15. The volatile memory device of claim 14 , wherein the test manager is configured to adjust a capacitance of the bit line by controlling, based on the test mode command, a number of the plurality of word lines that are driven.

16. The volatile memory device of claim 14 , wherein
the plurality of word lines include a plurality of dummy word lines that do not have addresses, and
the word line driver includes,
a first dummy word line driver configured to drive X dummy word lines among the plurality of dummy word lines, and
a second dummy word line driver configured to drive Y dummy word lines, among the plurality of dummy word lines, X and Y being integers greater than or equal to one.

17. The volatile memory device of claim 14 , wherein
the plurality of word lines include a plurality of normal word lines including a first normal word line or a second normal word line, the first normal word line being in a first area having ‘0’ as a most significant bit (MSB), and the second normal word line being in a second area having ‘1’ as the MSB, and
the test manager is configured to,
control driving of the second normal word line, when the first normal word line is in the first area, and
control driving of the first normal word line, when the first normal word line is in the second area.

18. The volatile memory device of claim 14 , wherein
each of the plurality of second memory cells include the first cell capacitor and a transistor, the transistor configured to switch the bit line, and
the test manager is configured to adjust a capacitance of the bit line by adjusting a voltage level of a word line driving voltage applied to the transistor.

19. A method of operating a volatile memory device, the volatile memory device including a first memory cell and a second memory cell, the first memory cell being connected to a bit line and the second memory cell being connected to one of a plurality of word lines, the method comprising:
receiving a test mode command including capacitance information;
driving N word lines of the plurality of word lines based on the test mode command, N being an integer greater than or equal to one; and
connecting a cell capacitor included in the second memory cell to the bit line connected to the first memory cell, the first memory cell being a memory cell to be tested.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Jin-Yong
• Kim Kyung-Ryun
• Kang Woong-Dai
• Yoon Hyun-Chul

Classifications

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title

• G11C2029/1202

  Word line control · CPC title

• G11C2029/1204

  Bit line control · CPC title

• G11C29/12 Primary

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G11C29/04

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title