Integrated circuit chip and die test without cell array

Patent metadata

Field	Value
Publication number	US-12009043-B2
Application number	US-201916667738-A
Country	US
Kind code	B2
Filing date	Oct 29, 2019
Priority date	Jan 3, 2019
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

An integrated circuit chip includes a first through electrode and a second through electrode formed through the integrated circuit chip, a transmission circuit suitable for selecting one of signals transmitted through the first and second through electrodes, respectively, and transmitting the selected signal to a data line, in response to a selection signal, and a selection signal generation circuit suitable for generating the selection signal by toggling the selection signal, during a test operation.

First claim

What is claimed is:

1. An integrated circuit chip comprising:
a data node configured to conduct integrated circuit chip signals;
a first through electrode and a second through electrode, both electrodes being formed through the integrated circuit chip;
a transmission circuit comprising:
a selection signal input; and
a selector comprising: a first data input coupled to the first through electrode, a second data input coupled to the second through electrode and a data output;
the transmission circuit being configured to selectively couple, one of the first and second through electrodes to the data node, in response to a selection signal, provided to the selection signal input;
the integrated circuit chip additionally comprising:
a selection signal generation circuit, which is configured to provide the selection signal responsive to an active state of at least one of: a test operation signal, a repair signal and a read data strobe signal; and
a read driver configured to couple the selector data output to one of two different data lines in response to the read data strobe signal,
wherein the selection signal generation circuit comprises:
a first NAND gate suitable for receiving a repair information signal and a test mode signal and performing a NAND operation on the received signals;
a second NAND gate suitable for receiving the divided signal and an inverted signal of the repair information signal and performing a NAND operation on the received signals; and
a third NAND gate suitable for receiving output signals of the first and second NAND gates, and generating the selection signal by performing a NAND operation on the received signals.

2. The integrated circuit chip of claim 1 , wherein, during a normal operation, the selection signal generation circuit activates or deactivates the selection signal based on repair information.

3. The integrated circuit chip of claim 1 , wherein the repair information signal is activated or deactivated according to whether a defect is detected in the first through electrode.

4. The integrated circuit chip of claim 1 , wherein the test mode signal is activated when the integrated circuit chip is subjected to a wafer level test.

5. The integrated circuit chip of claim 1 , further comprising:
a first latch unit and a second latch unit coupled to the first and second through electrodes, respectively, and configured to store data having different logic levels during the test operation.

6. The integrated circuit chip of claim 1 , wherein the integrated circuit chip comprises a base die of a high bandwidth memory (HBM).

7. An integrated circuit chip comprising:
a first data node and a second data node;
a first latch circuit and a second latch circuit configured to store data inputted through the first and second data nodes, respectively; and
a transmission circuit configured to alternately transmit data stored in the first and second latch circuits to the first data node in response to a selection signal, during a test operation, the transmission circuit comprising:
a selector having first and second data inputs, a selection signal input, and a data output, the selector configured to operatively connect one of the first and second data inputs to the data output responsive to its receipt of the selection signal; and
a read driver configured to couple a data signal output from the selector to the first data node in response to a read data strobe signal;
the integrated circuit chip additionally comprising:
a selection signal generation circuit, which is configured to provide the selection signal responsive to a test operation signal, a repair signal and a read data strobe signal.

8. The integrated circuit chip of claim 7 , wherein during the test operation, data having different logic levels are inputted through the first and second data nodes and stored in the first and second latch circuits.

9. The integrated circuit chip of claim 7 , further comprising:
a selection signal generation circuit configured to generate the selection signal based on repair information during a normal operation, and toggling the selection signal using a read data strobe signal during the test operation.

10. The integrated circuit chip of claim 9 , wherein the selection signal generation circuit comprises:
a first NAND gate suitable for receiving a repair information signal and a test mode signal and performing a NAND operation on the received signals;
a second NAND gate suitable for receiving a divided signal of the read data strobe signal and an inverted signal of the repair information signal and performing a NAND operation on the received signals; and
a third NAND gate suitable for receiving output signals of the first and second NAND gates, and generating the selection signal by performing a NAND operation on the received signals.

11. A memory device comprising:
a first integrated circuit chip; and
a plurality of second integrated circuit chips stacked over the first integrated circuit chip, wherein the first and second integrated circuit chips transmit/receive data through a plurality of through electrodes formed through the first integrated circuit chip and through the plurality of second integrated circuit chips,
wherein the first integrated circuit chip comprises:
a decoding circuit configured to generate a read data strobe signal by synchronizing a read command signal with a clock, during a read operation;
a divider circuit configured to generate a divided signal by dividing the read data strobe signal;
a transmission circuit comprising a selector having first and second data inputs, a selection signal input and a data output, the selector being configured to couple one of the first and second data inputs to the data output, in response to a selection signal received at the selection signal input; and
a read driver configured to couple a data signal output from the selector to one of two data lines, which are coupled to the first data node, in response to the read data strobe signal;
the memory device additionally comprising a selection signal generation circuit configured to provide the selection signal responsive to: a test operation signal, a repair signal and a read data strobe signal.

12. The memory device of claim 11 , wherein during a normal operation, the selection signal generation circuit activates or deactivates the selection signal based on repair information.

13. The memory device of claim 12 , wherein the repair information indicates whether a defect is present in the first through electrode.

14. The memory device of claim 11 , wherein the selection signal generation circuit comprises:
a first NAND gate suitable for receiving a repair information signal and a test mode signal and performing a NAND operation on the received signals;
a second NAND gate suitable for receiving a divided signal of a read data strobe signal and an inverted signal of the repair information signal and performing a NAND operation on the received signals; and
a third NAND gate suitable for receiving output signals of the first and second NAND gates, and generating the selection signal by performing a NAND operation on the received signals.

15. The memory device of claim 11 , wherein the first integrated circuit chip further comprising a first latch unit and a second latch unit coupled to the first and second through electrodes, respectively, and suitable for storing data having different logic levels during the test operation.

16. The memory device of claim 11 , wherein the memory device comprises a high bandwidth memory (HBM).

17. A

Assignees

• Sk Hynix Inc

Inventors

• Kim Ji-Hwan
• Oh Sang-Muk

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title