Pre-decoder circuitry
US-2024321327-A1 · Sep 26, 2024 · US
Mimicking multi-voltage domain wordline decoding logic for a memory array
US9196330B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9196330-B2 |
| Application number | US-201213424833-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 20, 2012 |
| Priority date | Jan 17, 2012 |
| Publication date | Nov 24, 2015 |
| Grant date | Nov 24, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.
First claim
Opening claim text (preview).
What is claimed is: 1. A multi-voltage domain control circuit for a memory array comprising: multi-voltage domain decoding logic configured to generate a wordline for the memory array; multi-voltage domain mimic logic configured to mimic the multi-voltage domain decoding logic to generate a dummy wordline; the multi-voltage domain decoding logic comprising: low voltage domain decoding logic; high voltage domain decoding logic; and high voltage domain final decoding logic…
Assignees
Inventors
Classifications
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9196330B2 cover?
- Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memor…
- Who is the assignee on this patent?
- Ge Shaoping, Chai Chiaming, Liles Stephen E, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G11C8/08. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).