Non-volatile memory device with first gate structure in memory cell region and second gate structure in peripheral circuit region and non-volatile memory system including the same

Patent metadata

Field	Value
Publication number	US-10026747-B2
Application number	US-201615239121-A
Country	US
Kind code	B2
Filing date	Aug 17, 2016
Priority date	Aug 19, 2015
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A non-volatile memory device is provided as follows. A substrate has a peripheral circuit. A first semiconductor layer is disposed on the substrate. The first semiconductor layer includes a memory cell region. A first gate structure is disposed on the first semiconductor layer. The first gate structure includes a plurality of first gate electrodes stacked in a perpendicular direction to the first semiconductor layer and a plurality of vertical channel structures penetrating the plurality of first gate electrodes. The first gate structure is arranged in the memory cell region. A second gate structure is disposed on the substrate. The second gate structure includes a plurality of second gate electrodes stacked in the perpendicular direction to the first semiconductor layer. The second gate structure is arranged outside the memory cell region.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a substrate having a peripheral circuit;
a first semiconductor layer disposed on the substrate, the first semiconductor layer comprising a first well region and a second well region which is separated from the first well region;
a first gate structure disposed on the first well region of the first semiconductor layer, the first gate structure comprising a plurality of first gate electrodes stacked in a perpendicular direction to the first semiconductor layer and a plurality of vertical channel structures penetrating the plurality of first gate electrodes; and
a second gate structure disposed on the second well region of the first semiconductor layer, the second gate structure comprising a plurality of second gate electrodes stacked in the perpendicular direction to the first semiconductor layer, the second gate structure being arranged outside the memory cell region,
wherein the first well region and the second well region are disposed on the peripheral circuit, and
wherein the entire first gate structure vertically overlaps the first well region and the entire second gate structure vertically overlaps the second well region.

2. The non-volatile memory device of claim 1 , wherein the second gate structure overlaps at least a portion of the peripheral circuit.

3. The non-volatile memory device of claim 1 , wherein the peripheral circuit includes a first peripheral circuit and a second peripheral circuit, and wherein the first gate structure overlaps the first peripheral circuit, and the second gate structure overlaps the second peripheral circuit.

4. The non-volatile memory device of claim 3 , wherein the first peripheral circuit comprises a row decoder providing a gate voltage to the first gate structure.

5. The non-volatile memory device of claim 3 , wherein the first peripheral circuit comprises a data input/output circuit transmitting data from the first gate structure to the outside of the non-volatile memory device.

6. The non-volatile memory device of claim 1 , wherein the second gate structure is spaced apart from one side of the first gate structure in a first direction in which the first gate structure extends.

7. The non-volatile memory device of claim 1 , wherein the second gate structure is spaced apart from one side of the first gate structure in a second direction in which the first gate structure extends, and wherein a length of the second gate structure in a first direction orthogonal to the second direction is substantially the same as a length of the first gate structure in the first direction.

8. The non-volatile memory device of claim 1 , wherein a height of the second gate structure is substantially equal to or less than a height of the first gate structure.

9. The non-volatile memory device of claim 1 , wherein the first gate structure constitutes a memory cell array, and the second gate structure constitutes a circuit element used for operations of the memory cell array.

10. The non-volatile memory device of claim 9 , wherein the second gate structure is configured to be a capacitor.

11. The non-volatile memory device of claim 9 , wherein the second gate structure is configured to be a test cell array for testing electrical properties of the first gate structure.

12. The non-volatile memory device of claim 1 , wherein the second gate structure comprises a plurality of pads, and wherein each of the plurality of pads extend from a corresponding gate electrode of the plurality of second gate electrodes to form a step shape.

13. The non-volatile memory device of claim 12 , wherein a first power supply voltage is applied to a pad of the plurality of pads, and a second power supply voltage is applied to another pad of the plurality of pads.

14. The non-volatile memory device of claim 12 , wherein the second gate structure further comprises vertical channel structures penetrating the plurality of second gate electrodes.

15. The non-volatile memory device of claim 14 , wherein an arrangement shape of the vertical channel structures of the second gate structure is different from an arrangement shape of the vertical channel structures of the first gate structure.

16. A non-volatile memory device comprising:
a substrate including a peripheral circuit;
a memory cell array disposed on the substrate and vertically overlapped with a first portion of the peripheral circuit in a perpendicular direction to the substrate, the memory cell array comprising a first gate structure; and
a second gate structure disposed on the substrate, the second gate structure being electrically isolated from the memory cell array and vertically overlapping a second portion of the peripheral circuit in the perpendicular direction to the substrate, and
wherein the first gate structure and the second gate structure are disposed on well regions separated from each other, and
wherein the first and second portions of the peripheral circuit are formed at a first level on the substrate and the well regions are formed at a second level on the substrate, and the first level is closer to the substrate than the second level.

17. The non-volatile memory device of claim 16 , wherein the second gate structure is arranged parallel to the first gate structure in a first direction parallel to the substrate.

18. The non-volatile memory device of claim 16 , wherein the second gate structure constitutes a circuit element.

19. The non-volatile memory device of claim 18 , wherein the circuit element comprises a test cell array.

20. A non-volatile memory system comprising:
the non-volatile memory device of claim 16 ; and
a memory controller which generates a control signal for controlling operations of the memory cell array based on data obtained from the second gate structure and provides the control signal to the non-volatile memory device.

21. The non-volatile memory device of claim 1 , wherein the first gate structure and the second gate structure are electrically connected to the peripheral circuit through a vertical contact penetrating through the first semiconductor layer, an insulating thin film and a wiring layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Chul-Jin
• Kwak Pan-Suk
• Ham Seok-Jun

Classifications

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title