Memory device and method of operating the memory device

Patent metadata

Field	Value
Publication number	US-11462285-B2
Application number	US-202117197957-A
Country	US
Kind code	B2
Filing date	Mar 10, 2021
Priority date	Sep 14, 2020
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell connected to a bit line;
a page buffer configured to store data to be stored in the memory cell; and
a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through the bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed,
wherein the page buffer comprises:
a test voltage transfer component configured to transfer the first test voltage or the second test voltage to the sensing node;
a sensing node connector configured to electrically connect the bit line and the sensing node; and
a sensing latch configured to latch a sensing value corresponding to the potential level of the sensing node and provide the sensing value to the test performer, and

wherein the test performer performs a precharge operation of changing the potential level of the sensing node from a second level to a first level higher than the second level after the first test voltage and the second test voltage are applied to the sensing node, and detects the defect of the sensing node in response to a change of the potential level of the sensing node to be less than a preset reference level from the first level.

2. The memory device of claim 1 , wherein the test performer is configured to control the page buffer to sequentially apply the first test voltage and the second test voltage of the level lower than the level of the first test voltage to the sensing node of the page buffer through the bit line, and detect the defect of the sensing node according to whether the potential level of the sensing node is changed, in response to a test command input from an external controller.

3. The memory device of claim 1 , wherein the test performer sequentially provides a bit line bias signal to the page buffer to apply the first test voltage to the sensing node and a bit line discharge signal to the page buffer to apply the second test voltage to the sensing node.

4. The memory device of claim 3 , wherein the test performer provides the bit line bias signal to the test voltage transfer component and then provides the bit line discharge signal to the test voltage transfer component.

5. The memory device of claim 3 , wherein the test performer provides the bit line discharge signal to the test voltage transfer component and then provides the bit line bias signal to the test voltage transfer component.

6. The memory device of claim 3 , wherein the test voltage transfer component provides the first test voltage to the bit line in response to the bit line bias signal, and provides the second test voltage to the bit line in response to the bit line discharge signal.

7. The memory device of claim 6 , wherein the test voltage transfer component comprises:
a bias transistor turned on in response to the bit line bias signal; and
a discharge transistor turned on in response to the bit line discharge signal.

8. The memory device of claim 7 , wherein the potential level of the sensing node is changed to the first level in response to a turn-on of the bias transistor and a turn-off of the discharge transistor, and is changed to the second level lower than the first level in response to a turn-off of the bias transistor and a turn-on of the discharge transistor.

9. The memory device of claim 1 , wherein the test performer provides a connection signal to connect the bit line and the sensing node to the sensing node connector.

10. A method of operating a memory device, the method comprising:
sequentially applying a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of a page buffer through a bit line; and
detecting a defect of the sensing node according to whether a potential level of the sensing node is changed to be less than a preset reference level,
wherein detecting the defect of the sensing node comprises:
performing a precharge operation of changing the potential level of the sensing node from a second level to a first level higher than the second level after the first test voltage and the second test voltage are applied to the sensing node; and
detecting the defect of the sensing node in response to a change of the potential level of the sensing node to be less than the preset reference level from the first level.

11. The method of claim 10 , wherein applying the first test voltage and the second test voltage to the sensing node comprises:
providing a bit line bias signal to the page buffer to apply the first test voltage to the sensing node of the page buffer; and
providing a bit line discharge signal to the page buffer to apply the second test voltage to the sensing node of the page buffer after the bit line bias signal is provided.

12. The method of claim 10 , wherein applying the first test voltage and the second test voltage to the sensing node comprises:
providing a bit line discharge signal to the page buffer to apply the second test voltage to the sensing node of the page buffer; and
providing a bit line bias signal to the page buffer to apply the first test voltage to the sense node of the page buffer after the bit line discharge signal is provided.

13. The method of claim 10 , wherein the potential level of the sensing node is changed to the first level as the first test voltage is applied, and is changed to the second level lower than the first level as the second test voltage is applied.

Assignees

• Sk Hynix Inc

Inventors

• Lim Sungmook
• Yang In Gon
• Shin Jae Hyeon
• Choi Hyung Jin

Classifications

• G11C29/026 Primary

  in sense amplifiers · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C29/1201

  comprising I/O circuitry · CPC title

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title