Selectively transparent bridge for peripheral component interconnect express bus systems

Patent metadata

Field	Value
Publication number	US-9244874-B2
Application number	US-201313918685-A
Country	US
Kind code	B2
Filing date	Jun 14, 2013
Priority date	Jun 14, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

First claim

We claim:

1. A system comprising:
a PCIe (Peripheral Component Interconnect Express) subsystem comprising PCIe devices;
a host system; and
a bus extender coupling the host system to the PCIe subsystem, and configured to:
create a virtual bus topology corresponding to an actual bus topology of the PCIe subsystem;
selectively hide one or more devices of the PCIe devices from the host system by omitting the one or more devices from the virtual bus topology, resulting in the one or more devices being hidden from the host system, and remaining devices of the PCIe devices being visible to the host system;
make the virtual bus topology apparent to the host system during configuration of the PCIe devices;
intercept configuration packets generated by the host system based on the virtual bus topology for configuring the visible remaining devices; and
configure the selectively hidden one or more devices and the visible remaining devices according to the actual bus topology, and based at least partially on contents of the intercepted configuration packets.

2. The system of claim 1 , wherein the bus extender is further configured to manage the selectively hidden one or more devices.

3. The system of claim 1 , wherein the bus extender is further configured to generate and transmit to the PCIe devices downstream configuration packets based at least on the intercepted configuration packets to configure the PCIe devices.

4. The system of claim 1 , wherein the bus extender appears to the host system as a PCI-to-PCI bridge.

5. The system of claim 1 , wherein the host system is configured to generate the configuration packets according to PCI bus configuration mechanisms.

6. The system of claim 1 , wherein the bus extender is further configured to convert the virtual bus topology into the actual bus topology by translating target BDFs (bus, device, function), and performing additional tasks to program the selectively hidden one or more devices.

7. A configuration block for configuring a PCIe (Peripheral Component Interconnect Express) subsystem that comprises PCIe devices coupled to a host system, the configuration block comprising:
an interface for transmitting and receiving PCIe packets to and from the PCIe subsystem and the host system; and
a processing element configured to:
create a virtual bus topology corresponding to an actual bus topology of the PCIe subsystem;
selectively hide a subset of the PCIe devices from the host system by omitting the subset of the PCIe devices from the virtual bus topology, resulting in the subset of the PCIe devices being hidden from the host system, and remaining devices of the PCIe devices being visible to the host system;
make the virtual bus topology apparent to the host system during configuration of the PCIe devices;
intercept configuration packets generated by the host system based on the virtual bus topology for configuring the visible remaining devices; and
configure the selectively hidden subset of the PCIe devices and the visible remaining devices according to the actual bus topology, and based at least partially on contents of the intercepted configuration packets.

8. The configuration block of claim 7 , wherein the processing element is further configured to manage the selectively hidden subset of the PCIe devices.

9. The configuration block of claim 7 , wherein the processing element is further configured to generate and provide, to the interface, downstream configuration packets based at least partially on the intercepted configuration packets; and
wherein the interface is configured to transmit the generated downstream configuration packets to the PCIe subsystem to configure the PCIe devices.

10. The configuration block of claim 7 , wherein the configuration block is comprised in a bus extender that appears to the host system as a PCI-to-PCI bridge.

11. The configuration block of claim 7 , wherein the processing element is configured to convert the virtual bus topology into the actual bus topology by translating target BDFs (bus, device, function), and performing additional tasks to program the selectively hidden subset of the PCIe devices.

12. A method for configuring and operating PCIe (Peripheral Component Interconnect Express) devices comprised in a PCIe subsystem coupled to a host system, the method comprising:
creating a virtual bus topology corresponding to an actual bus topology of the PCIe subsystem;
selectively hiding a subset of the PCIe devices from the host system by not including in the virtual bus topology the subset of the PCIe devices, while including in the virtual bus topology remaining ones of the PCIe devices not included in the subset of the PCIe devices;
making the virtual bus topology apparent to the host system during configuration of the PCIe devices;
intercepting configuration packets transmitted by the host system to the remaining ones of the PCIe devices; and
configuring the PCIe devices according to the actual bus topology, and based at least partially on contents of the intercepted configuration packets.

13. The method of claim 12 , further comprising:
managing the selectively hidden subset of the PCIe devices by a local processing element separate from a primary processing element of the host system.

14. The method of claim 13 , further comprising relaying message type PCIe packets through the local processing element to provide a path for legacy interrupt messages.

15. The method of claim 12 , wherein said configuring the PCIe devices comprises:
generating downstream configuration packets based on the actual bus topology and at least partially based on the intercepted configuration packets; and
transmitting the downstream configuration packets to the PCIe devices.

16. The method of claim 12 , further comprising:
converting the virtual bus topology into the actual bus topology by translating target BDFs (bus, device, function); and
performing additional tasks to program the selectively hidden subset of the PCIe devices.

17. The method of claim 12 , further comprising:
generating, by the host, the configuration packets according to resource request information stored in a configuration space register.

18. The method of claim 17 , further comprising:
writing, by a local processing element separate from a primary processing element of the host system, the resource request information into the configuration space register.

Assignees

• Nat Instr Corp

Inventors

• Hearn Jonathan W
• Jones Craig S
• Ross Robert D

Classifications

• G06F13/4045 Primary

  where the bus bridge performs an extender function · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/36

  for access to common bus or bus system · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title