Coherent fabric interconnect for use in multiple topologies

Patent metadata

Field	Value
Publication number	US-2016378701-A1
Application number	US-201514751899-A
Country	US
Kind code	A1
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.

First claim

We claim:

1 . A semiconductor device comprising:
mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, the fabric comprising:
logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.

2 . The semiconductor device defined in claim 1 wherein the logic controls state of one or more cache memories and at least one data buffer and the type and timing of requests on memory, and controls timing of responses to the requests.

3 . The semiconductor device defined in claim 2 wherein the logic responds to software initiated transactions to ensure that software initiated cache control and ordering events are handled.

4 . The semiconductor device defined in claim 1 wherein the plurality of modes comprises:
a first mode in which a memory controller is connected to the first fabric;
a second mode in which a memory controller is connected to a non-coherent input/output (I/O) fabric connected to the first fabric; and
a third mode in which an intellectual property (IP) core is connected to a memory controller connected to a non-coherent input/output (I/O) fabric connected to the first fabric.

5 . The semiconductor device defined in claim 1 wherein the logic causes all write operations to memory to be posted without waiting for a completion response in a first of the plurality of modes and causes writes to be sent as posted or non-posted with a completion response required in one or more other of the plurality of modes.

6 . The semiconductor device defined in claim 1 wherein the logic allows cached and uncached write operations to memory to be reordered in a first of the plurality of modes and only allows cached write operations to be reordered in a second of the plurality of modes.

7 . The semiconductor device defined in claim 1 wherein the logic does not complete one or more of fence or cache invalidate operations until one or more prior write combining write operations, non-temporal write operations or cache line flush operations to memory have received their completion responses in one or more of the plurality of modes and does not trigger any action by the fabric in another of the plurality of modes.

8 . The semiconductor device defined in claim 1 wherein the logic does not forward uncacheable write operations to either memory or an input/output (I/O) fabric until one or more prior write combining write operations or non-temporal write operations to memory have received their completion responses in one or more of the plurality of modes and does not trigger any action by the fabric in another of the plurality of modes.

9 . The semiconductor device defined in claim 1 wherein the mode memory is located in the first fabric.

10 . The semiconductor device defined in claim 1 wherein the mode memory is set via BIOS, firmware, strap, fuse or software.

11 . The semiconductor device defined in claim 1 wherein the mode is set based on an address of a memory request received by the fabric.

12 . The semiconductor device defined in claim 1 wherein the mode is set based on a mode of the processing unit.

13 . The semiconductor device defined in claim 1 wherein the mode is set based on a virtual machine identifier (ID).

14 . A system comprising:
a semiconductor device having
mode memory to store information indicative of one of the plurality of modes;
a first fabric operable in a plurality of modes, the fabric comprising logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative of one of the plurality of modes; and
at least one memory controller coupled to the semiconductor device; and at least one memory coupled to the at least one memory controller.

15 . The system defined claim 14 wherein the logic controls state of one or more cache memories and at least one data buffer and the type and timing of request on memory, and controls timing of responses to the requests.

16 . The system defined in claim 15 wherein the logic responds to software initiated transactions to ensure that software initiated cache control and ordering events are handled.

17 . The system defined in claim 14 wherein the plurality of modes comprises:
a first mode in which a memory controller is connected to the first fabric;
a second mode in which a memory controller is connected to a non-coherent input/output (I/O) fabric connected to the first fabric; and
a third mode in which an intellectual property (IP) core is connected to a memory controller connected to a non-coherent input/output (I/O) fabric connected to the first fabric.

18 . The system defined in claim 14 where the at least one memory comprises a dynamic random access memory (DRAM), a static RAM (SRAM), or both a DRAM and an SRAM.

19 . The system defined in claim 14 wherein the logic causes all write operations to memory to be posted without waiting for a completion response in a first of the plurality of modes and causes write operations to be sent as posted or non-posted with a completion response required in one or more other of the plurality of modes.

20 . The system defined in claim 14 wherein the logic allows cached and uncached write operations to memory to be reordered in a first of the plurality of modes and only allows cached write operations to be reordered in a second of the plurality of modes.

21 . The system defined in claim 14 wherein the logic does not complete one or more of fence or cache invalidate operations until one or more prior write combining write operations, non-temporal write operations or cache line flush operations to memory have received their completion responses in one or more of the plurality of modes and does not trigger any action by the fabric in another of the plurality of modes.

22 . The semiconductor system defined in claim 14 wherein the logic does not forward uncacheable write operations to either memory or an input/output (I/O) fabric until one or more prior write combining write operations or non-temporal write operations to memory have received their completion responses in one or more of the plurality of modes and does not trigger any action by the fabric in another of the plurality of modes.

23 . The system defined in claim 14 wherein the mode memory is located in the first fabric.

24 . The system defined in claim 14 wherein the mode memory is set via BIOS, firmware, strap, fuse or software.

25 . A method comprising:
reading mode memory to determine a mode in which a first fabric of a semiconductor device is to run; and handling ordering and coherency for read and write operations received by the fabric based on the mode identified by reading the mode memory.

26 . The method defined in claim 25 wherein the plurality of modes comprises:
a first mode in which a memory controller is connected to the first fabric;
a second mode in which a memory controller is connected to a non-coherent input/output (I/O) fabric connected to the first fabric; and
a third mode in which an intellectual property (IP) core is connected to a memory controller connected to a non-coherent input/output (I/O) fabric connected to the first fabric.

Assignees

• Intel Corp

Inventors

• Niell Jose S
• Cutter Daniel F
• Robinson Stephen J
• Patel Mukesh K

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F2212/1048

  Scalability · CPC title