Highly regular logic design for efficient 3D integration

Patent metadata

Field	Value
Publication number	US-12557392-B2
Application number	US-202217880321-A
Country	US
Kind code	B2
Filing date	Aug 3, 2022
Priority date	Jul 29, 2019
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, where each contact is electrically coupled to a corresponding electrical node of the cell circuitry.

First claim

The invention claimed is:

1 . An integrated circuit comprising:
unit cells arranged in an array, each unit cell comprising: field effect transistors arranged in a stack; local interconnect structures comprising select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within the unit cell; and an array of contacts disposed on an accessible surface of the unit cell, each contact being electrically coupled to a corresponding electrical node of the cell circuitry, wherein: the unit cells each have a common footprint and are positioned in the array so that diffusion breaks embracing the cell circuitry of each unit cell align with the diffusion breaks in adjacent unit cells to form continuous spaces that extend across all unit cells in respective columns of the array, and the integrated circuit further comprising power contacts disposed in the continuous spaces, wherein the power contacts extend vertically from a substrate to the accessible surface of the unit cells and form power walls that provide electrical power to at least the unit cells in the respective columns of the array, and wherein the power walls extend lengthwise in a direction parallel to a length of the diffusion breaks.

2 . The integrated circuit of claim 1 , further comprising a functionalization layer comprising electrically conductive wiring segments formed between select contacts on respective accessible surfaces of one or more unit cells in the array.

3 . The integrated circuit of claim 1 , wherein surfaces of the power contacts are exposed on the accessible surface of each unit cell in the respective columns of the array.

4 . The integrated circuit of claim 1 , wherein surfaces of the respective power contacts are connected to buried power rails.

5 . The integrated circuit of claim 1 , wherein the cell circuitry is identical across all unit cells in the array.

6 . The integrated circuit of claim 5 , wherein the cell circuitry is constructed from front end-of-line and middle end-of-line structures that extend across the unit cells.

7 . The integrated circuit of claim 6 , wherein the front-end of line and middle-end of line processes include multiplication patterning processes.

8 . The integrated circuit of claim 7 , wherein the multiplication patterning processes include directed self-assembly and/or self-aligned double patterning.

9 . The integrated circuit of claim 1 , wherein the field effect transistors are stacked in complementary pairs.

10 . The integrated circuit of claim 9 , wherein gates of each of the complementary pairs of field effect transistors are electrically connected to one another.

11 . The integrated circuit of claim 10 , wherein the complementary pairs in the stack of field effect transistors is greater than one in number.

12 . The integrated circuit of claim 1 , wherein the field effect transistors are stacked in planes that are parallel to the accessible surface.

13 . The integrated circuit of claim 1 , wherein the integrated circuit is monolithic.

14 . The integrated circuit of claim 1 , wherein:
the unit cells comprise a first unit cell in abutment with a second unit cell; and at least one metal strap connecting a contact of the first unit cell to a contact of the second unit cell to form a synthesis logic circuit from the first and second unit cells.

15 . The integrated circuit of claim 14 , wherein the first and second unit cells are either in vertical abutment in a column of the array to form the logic circuit as a relatively tall standard cell, or in horizontal abutment in a row of the array to form the logic circuit as a relatively wide standard cell.

16 . The integrated circuit of claim 2 , wherein the electrically conductive wiring segments are unidirectional.

17 . An integrated circuit comprising:
electrical contacts disposed across a surface beneath which identical unit cells are constructed, each unit cell comprising: transistors arranged in a stack, and local interconnect structures comprising select conductive paths between select terminals of the transistors to define cell circuitry that is confined within the unit cell, wherein select nodes of the cell circuitry are connected to the electrical contacts disposed over the stack of transistors of each unit cell; and power contacts disposed in continuous spaces between groups of the unit cells, wherein the power contacts extend vertically from a substrate to a surface of the unit cells and form power walls that provide electrical power to at least the unit cells in the corresponding group thereof, and wherein the power walls extend lengthwise in a direction parallel to a length of diffusion breaks that form the continuous spaces.

18 . The integrated circuit of claim 17 , further comprising a functionalization layer including electrically conductive wiring segments formed between select ones of the electrical contacts.

19 . The integrated circuit of claim 17 , wherein select ones of the local interconnect structures are connected to at least one of the power contacts.

20 . The integrated circuit of claim 17 , wherein the transistors are stacked in planes that are parallel to the surface on which the electrical contacts are disposed.

Assignees

• Tokyo Electron Ltd

Inventors

• Liebmann Lars
• Smith Jeffrey
• Chanemougame Daniel
• Devilliers Anton

Classifications

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title