Standard cell architecture for diffusion based on fin count

Patent metadata

Field	Value
Publication number	US-10236302-B2
Application number	US-201715629725-A
Country	US
Kind code	B2
Filing date	Jun 21, 2017
Priority date	Jun 22, 2016
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

Disclosed systems and methods pertain to finfet based integrated circuits designed with logic cell architectures which support multiple diffusion regions for n-type and p-type diffusions. Different diffusion regions of each logic cell can have different widths or fin counts. Abutting two logic cells is enabled based on like fin counts for corresponding p-diffusion regions and n-diffusion regions of the two logic cells. Diffusion fills are used at common edges between the two logic cells for extending lengths of diffusion, based on the like fin counts. The logic cell architectures support via redundancy and the ability to selectively control threshold voltages of different logic cells with implant tailoring. Half-row height cells can be interleaved with standard full-row height cells.

First claim

What is claimed is:

1. An apparatus comprising:
an integrated circuit designed with finfet based logic cells, wherein the integrated circuit comprises at least a first logic cell, wherein the first logic cell comprises at least one of:
two or more p-diffusion regions, stacked in a y-direction, with each of the two or more p-diffusion regions comprising two or more fins in an x-direction, and each of the two or more p-diffusion regions comprising an island with p-type doping in an n-type well; or
two or more n-diffusion regions, stacked in the y-direction, with each of the two or more n-diffusion regions comprising two or more fins in the x-direction, and each of the two or more n-diffusion regions comprising an island with n-type doping in a p-type well.

2. The apparatus of claim 1 , wherein the first logic cell comprises at least one of:
a first p-diffusion region and a second p-diffusion region, the first p-diffusion region and the second p-diffusion region having different fin counts; or
a first n-diffusion region and a second n-diffusion region, the first n-diffusion region and the second n-diffusion region having different fin counts.

3. The apparatus of claim 1 , further comprising a distributed power rail network comprising at least one of:
at least a first local power rail associated with at least one of the two or more p-diffusion regions; or
at least a second local power rail associated with at least one of the two or more n-diffusion regions.

4. The apparatus of claim 3 , wherein, at least one of:
the first local power rail is dedicated to the at least one of the two or more p-diffusion regions; or
the second local power rail is dedicated to the at least one of the two or more n-diffusion regions.

5. The apparatus of claim 1 , wherein the first logic cell comprises at least one of:
a first p-diffusion region and a second p-diffusion region, the first p-diffusion region and the second p-diffusion region formed with different levels of p-type implants; or
a first n-diffusion region and a second n-diffusion region, the first n-diffusion region and the second n-diffusion region formed with different levels of n-type implants.

6. The apparatus of claim 1 , wherein the first logic cell further comprises at least one of:
a first pfet formed in a first p-diffusion region and a second pfet formed in a second p-diffusion region, the first pfet and the second pfet having different threshold voltages or channel lengths; or
a first nfet formed in a first n-diffusion region and a second nfet formed in a second n-diffusion region, the first nfet and the second nfet having different threshold voltages or channel lengths.

7. The apparatus of claim 1 , wherein the integrated circuit further comprises a second logic cell, wherein the first logic cell and the second logic cell each comprise:
at least one p-diffusion region with a first fin count; or
at least one n-diffusion region with a second fin count.

8. The apparatus of claim 7 , wherein the first logic cell has a first logic cell boundary and the second logic cell has a second logic cell boundary, and wherein the first logic cell is abutted with the second logic cell at a common edge between the first logic cell boundary and the second logic cell boundary, and
wherein the first logic cell comprises at least one pfet formed on a first p-diffusion region with the first fin count and at least one nfet formed on a first n-diffusion region with the second fin count, and
wherein the second logic cell comprises at least one pfet formed on a second p-diffusion region with the first fin count and at least one nfet formed on a second n-diffusion region with the second fin count.

9. The apparatus of claim 8 , wherein the integrated circuit further comprises at least one of:
a first p-diffusion fill to traverse the common edge and join the first p-diffusion region of the first logic cell and the second p-diffusion region of the second logic cell; or
a first n-diffusion fill to traverse the common edge and join the first n-diffusion region of the first logic cell and the second n-diffusion region of the second logic cell.

10. The apparatus of claim 9 , wherein at least one of:
the first p-diffusion region of the first logic cell and the second p-diffusion region of the second logic cell are of a common first potential; or
the first n-diffusion region of the first logic cell and the second n-diffusion region of the second logic cell are of a common second potential.

11. The apparatus of claim 10 , wherein the integrated circuit further comprises at least one of:
a connection between the first p-diffusion fill and a first metal layer at the common first potential; or
a connection between the first n-diffusion fill and a second metal layer at the common second potential.

12. The apparatus of claim 11 , wherein the common first potential corresponds to a potential of a power rail, and the common second potential corresponds to a potential of a ground rail or a local interconnect.

13. The apparatus of claim 12 , wherein at least one of the power rail or the ground rail are distributed in a space between the diffusion regions of the first logic cell and the second logic cell.

14. The apparatus of claim 8 , wherein the integrated circuit further comprises at least one poly line of the first logic cell or the second logic cell at a floating potential, the at least one poly line adjacent to the common edge and intersecting at least one of the first p-diffusion region, the second p-diffusion region, the first n-diffusion region, or the second n-diffusion region.

15. The apparatus of claim 8 , wherein the first logic cell is a 2-input NAND gate with a ratio logic wherein the first fin count is different from the second fin count.

16. The apparatus of claim 15 , wherein the 2-input NAND gate comprises
two pfets connected in parallel, with each of the two pfets having the first fin count equal to two fins formed on the first p-diffusion region; and
two nfets in series, with each of the two nfets having the second fin count equal to four fins, with two of the four fins formed on the first n-diffusion region and two of the four fins formed on another n-diffusion region of the first logic cell connected in series with the first n-diffusion region.

17. The apparatus of claim 16 , wherein the integrated circuit further comprises at least one poly line shared between the two pfets and the two nfets.

18. The apparatus of claim 16 , wherein the integrated circuit further comprises a poly cut on at least one poly line between the first p-diffusion region and another p-diffusion of the first logic cell.

19. The apparatus of claim 16 , wherein the integrated circuit further comprises at least one gate via on at least one poly line between the two pfets and the two nfets.

20. The apparatus of claim 19 , wherein the integrated circuit further comprises a metal to diffusion (MD) layer connected to the at least one gate via.

21. The apparatus of claim 15 , wherein the second logic cell is an inverter comprising two pfets, with each pfet having the first fin count equal to two fins and formed in two p-diffusion regions including at least the second p-diffusion region; and two nfets, with each nfet having the second fin count equal to two fins and formed in two n-diffusion regions including at least the second n-diffusion region.

22. An apparatus comprising an integrated circuit designed with finfet based logic cells, the integrated circ

Assignees

• Qualcomm Inc

Inventors

• Correale Jr Anthony
• Bowers Benjamin
• DELLA ROVA Tracey
• Goodall Iii William

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title