Semiconductor device including standard cells

Patent metadata

Field	Value
Publication number	US-2019148407-A1
Application number	US-201815940191-A
Country	US
Kind code	A1
Filing date	Mar 29, 2018
Priority date	Nov 14, 2017
Publication date	May 16, 2019
Grant date	—

Abstract

A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

First claim

What is claimed is:

1 . A semiconductor device including a plurality of standard cells, wherein:
the plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction, the first group of standard cells and the second group of standard cells are arranged in a column direction, and a cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

2 . The semiconductor device of claim 1 , wherein:
each of the plurality of standard cells includes a first power supply wiring for supplying a first potential and a second power supply wiring for supplying a second potential different from the first potential, and a cell height of each of the plurality of standard cells is a distance in the column direction between a center line, extending in the row direction, of the first power supply wiring and a center line, extending in the row direction, of the second power supply wiring.

3 . The semiconductor device of claim 2 , wherein a ratio of the cell height of the first group of standard cells and the cell height of the second group of standard cells is N:M, where N and M are different natural numbers.

4 . The semiconductor device of claim 2 , wherein one of the first power supply wiring and the second power supply wiring of the first group of standard cells is shared by the second group of standard cells.

5 . The semiconductor device of claim 4 , wherein each of the plurality of standard cells includes active fin structures extending in the row direction, and forming one or more fin field effect transistors (FinFETs).

6 . The semiconductor device of claim 5 , wherein in the first group of standard cells, the active fin structures are aligned with either one of only I virtual lines extending in the row direction, respectively, where I is a natural number of two or more.

7 . The semiconductor device of claim 6 , wherein in the second group of standard cells, the active fin structures are aligned with either one of only J virtual lines extending in the row direction, respectively, where J is a natural number of two or more and different from I.

8 . The semiconductor device of claim 7 , wherein either of I or J is two.

9 . The semiconductor device of claim 5 , wherein each of the plurality of standard cells further includes one or more dummy fin structures extending in the row direction, not functioning as a FinFET.

10 . The semiconductor device of claim 9 , wherein:
one of the one or more dummy fin structures is located between two of the active fin structures, and the one of the one or more dummy fin structures and the two of the active fin structures are arranged with a constant pitch in the column direction.

11 . The semiconductor device of claim 5 , wherein:
each of the plurality of standard cells further includes dummy fin structures extending in the row direction, not functioning as a FinFET, and one of the dummy fin structures is located under the first power supply wiring, and one of the dummy fin structures is located under the second power supply wiring.

12 . The semiconductor device of claim 11 , wherein at least one of a height and a width of the dummy fin structures is different from that of the active fin structures.

13 . The semiconductor device of claim 4 , wherein:
each of the plurality of standard cells has a p-type device region and an n-type device region, and the first group of standard cells and the second group of standard cells are arranged in the column direction such that the p-type region of the first group of standard cells and the p-type region of the second group of standard cells are located between the n-type region of the first group of standard cells and the n-type region of the second group of standard cells.

14 . The semiconductor device of claim 13 , wherein:
each of the plurality of standard cells includes active fin structures extending in the row direction, and forming one or more fin field effect transistors (FinFETs), and in the first group of standard cells, a number of the active fin structures included in the p-type region is different from a number of the active fin structures included in the n-type region.

15 . The semiconductor device of claim 14 , wherein in the second group of standard cells, a number of the active fin structures included in the p-type region is equal to a number of the active fin structures included in the n-type region.

16 . The semiconductor device of claim 4 , wherein each of the plurality of standard cells includes metal wirings extending in the row direction, and located at a level closer to a substrate than a level at which the first and second power supply wirings are located.

17 . The semiconductor device of claim 16 , wherein in the first group of standard cells, the metal wirings are aligned with either one of only K virtual lines extending in the row direction, respectively, where K is a natural number of two or more.

18 . The semiconductor device of claim 17 , wherein in the second group of standard cells, the metal wirings are aligned with either one of only L virtual lines extending in the row direction, respectively, where L is a natural number of two or more and different from K.

19 . A semiconductor device including a plurality of standard cells, wherein:
the plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction, the first group of standard cells and the second group of standard cells are arranged in a column direction, a cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells, and the cell height of the first group of standard cells and the cell height of the second group of standard cells are determined based on a number of fin structures arranged along the column direction within each of plurality of standard cells.

20 . A semiconductor device including a plurality of standard cells, wherein:
the plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction, the first group of standard cells and the second group of standard cells are arranged in a column direction, each of the plurality of standard cells includes a first power supply wiring for supplying a first potential and a second power supply wiring for supplying a second potential different from the first potential, a cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction, and the cell height of the first group of standard cells and the cell height of the second group of standard cells are determined based on a number of metal wirings arranged along the column direction within each of plurality of standard cells, the metal wirings being located at a level closer to a substrate than a level at which the first and second power supply wirings are located.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Guo Ta-Pen
• Diaz Carlos H
• Lu Lee-Chung
• Tien Li-Chun

Classifications

• H01L2027/11887

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L2027/11881

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L27/11807 Primary

  Electricity · mapped topic