Three-dimensional semiconductor device and method of fabrication

Patent metadata

Field	Value
Publication number	US-9997598-B2
Application number	US-201715671771-A
Country	US
Kind code	B2
Filing date	Aug 8, 2017
Priority date	Aug 8, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate;
a gate region of a field effect transistor formed on the substrate, the gate region including vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate, a given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically; and
a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region, wherein a first gate electrode has a step-shaped profile and connects to a first-level nanowire.

2. The semiconductor device of claim 1 , wherein the semiconductor device includes a barrier layer positioned between the at least two nanowires that are vertically aligned, wherein the barrier layer was selectively deposited on a first material without being deposited on a second material.

3. The semiconductor device of claim 2 , wherein the barrier layer was initially selectively deposited on a temporary surface covering a lower nanowire and extending between the lower nanowire and an upper nanowire vertically aligned above the lower nanowire, without the barrier layer being deposited on the upper nanowire.

4. The semiconductor device of claim 1 , wherein electrical contacts for each gate electrode above the gate region are adjacent to each other.

5. The semiconductor device of claim 1 , wherein the step-shaped connecting structure includes a second gate electrode positioned above a horizontal segment of the first gate electrode and connected to a second-level nanowire.

6. The semiconductor device of claim 1 , wherein the step-shaped connecting structure includes a second gate electrode connecting to a second-level nanowire, the second-level nanowire positioned above the first-level nanowire, the second gate electrode positioned above a horizontal surface of the first gate electrode, the first gate electrode and the second gate electrode being separated by one or more dielectric films.

7. The semiconductor device of claim 1 , wherein each nanowire is spatially and electrically separated from each other.

8. The semiconductor device of claim 1 , wherein the first gate electrode has a horizontally extending member and a vertically extending member; and
wherein the connecting structure includes a second gate electrode positioned above the horizontally extending member and adjacent to the vertically extending member, with the first gate electrode being electrically separated from the second gate electrode.

9. The semiconductor device of claim 1 , wherein the p-type nanowire is an n-channel metal-oxide-semiconductor (NMOS) field-effect transistor; and
wherein the n-type nanowire is a p-channel metal-oxide-semiconductor (PMOS) field-effect transistor.

10. The semiconductor device of claim 9 , wherein the n-type nanowire is positioned on a first nanowire level; and
wherein p-type nanowire is positioned on a second nanowire level above the first nanowire level.

11. The semiconductor device of claim 1 , wherein at least one nanowire level includes two vertically stacked nanowires of a same semiconductor channel type.

12. The semiconductor device of claim 1 , wherein the semiconductor device is an SRAM device.

13. The semiconductor device of claim 1 , wherein the semiconductor device is a programmable logic device.

14. The semiconductor device of claim 1 , wherein the semiconductor device is a random logic device.

15. The semiconductor device of claim 1 , wherein the semiconductor device is a combination device having SRAM cells positioned over random logic cells.

16. A method of forming a semiconductor device, the method comprising: forming nanowires extending through a gate region of a field-effect transistor device;
forming a horizontal barrier layer between two vertically separated nanowires within the gate region, the gate region having a temporary fill material covering a first-level nanowire, the temporary fill material having a horizontal surface extending between the first-level nanowire and a second-level nanowire, the second-level nanowire positioned above the first level-nanowire and vertically aligned with the first-level nanowire, the horizontal barrier being formed by selectively depositing barrier material on the temporary surface without depositing barrier material on the second-level nanowire;
forming a vertical electrode barrier extending to the horizontal barrier; and
forming a first gate electrode and a second gate electrode within the gate region, with each gate electrode electrically connecting a nanowire to a contact location above the gate region, the first gate electrode having a step-shaped profile, the first and second gate electrode being separated from each other by at least the horizontal barrier and the vertical electrode barrier.

17. The method of claim 16 , wherein forming the nanowires includes forming an n-type nanowire vertically above a corresponding p-type nanowire.

18. The method of claim 16 , wherein forming the nanowires includes forming an p-type nanowire vertically above a corresponding n-type nanowire.

19. The method of claim 16 , wherein forming nanowires includes forming, fins having alternating layers of a first material and a second material; and
selectively removing the first material such that the second material remains as nanowires.

20. A method of forming a semiconductor device, the method comprising:
forming a gate region having a vertical stack of nanowires that includes at least two nanowires with longitudinal axes oriented horizontally and with the nanowires being spaced apart from each other and aligned vertically;
executing a process sequence of depositing temporary fill material in the gate region;
recessing the temporary fill material to a location in between vertically stacked nanowires;
forming a horizontal barrier material by selectively depositing on the temporary fill material without depositing on uncovered nanowires;
forming vertical barriers;
selectively metallizing nanowires; and
forming first and second gate electrodes by depositing metal within spaces defined by the horizontal barrier and vertical barriers.

Assignees

• Tokyo Electron Ltd

Inventors

• Smith Jeffrey
• Devilliers Anton
• Mohanty Nihar
• Kal Subhadeep
• Tapily Kandabara

Classifications

• H01L29/42392

  Electricity · mapped topic

• H01L21/823878

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L21/823871

  Electricity · mapped topic

• H01L27/1104

  Electricity · mapped topic