Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

Patent metadata

Field	Value
Publication number	US-10170404-B2
Application number	US-201715630685-A
Country	US
Kind code	B2
Filing date	Jun 22, 2017
Priority date	Aug 31, 2015
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

First claim

What is claimed is:

1. A method, comprising:
forming a first interconnect structure over a first substrate, wherein the first interconnect structure includes a plurality of first interconnect elements;
forming a second substrate over the first substrate such that the first interconnect structure is disposed between the first substrate and the second substrate;
forming a via that extends vertically through the second substrate, wherein the via is formed to be electrically coupled to the first interconnect structure; and
forming a dummy gate over the second substrate, wherein the dummy gate is formed to be electrically coupled to the via.

2. The method of claim 1 , further comprising: forming a first circuit cell at least partially in the second substrate and forming a second circuit cell at least partially in the second substrate, and wherein the dummy gate is formed between the first circuit cell and the second circuit cell.

3. The method of claim 2 , wherein the first circuit cell and the second circuit cell are formed to be adjacent to each other, and wherein the dummy gate is not formed to be at an edge of the first circuit cell or an edge of the second circuit cell.

4. The method of claim 2 , wherein the dummy gate is formed to not serve as a functional part of either the first circuit cell or the second circuit cell.

5. The method of claim 1 , wherein the forming of the dummy gate comprises forming an electrically-floating gate.

6. The method of claim 5 , wherein the forming of the electrically-floating gate is performed such that the electrically-floating gate is not electrically coupled to a power supply rail.

7. The method of claim 1 , wherein the forming the via and the forming the dummy gate are performed such that the dummy gate is electrically coupled to at least one of the first interconnect elements.

8. The method of claim 1 , further comprising: forming a second interconnect structure over the second substrate, the second interconnect structure including a plurality of second interconnect elements.

9. The method of claim 8 , wherein the forming of the second interconnect structure comprises electrically coupling the dummy gate with at least one of the second interconnect elements.

10. The method of claim 1 , further comprising: forming doped regions in the second substrate, wherein the forming of the via is performed such that the via does not extend through any of the doped regions in the second substrate.

11. The method of claim 1 , wherein the forming of the second substrate comprises forming the second substrate using a deposition process, and wherein the second substrate is formed to be thinner than the first substrate.

12. A method, comprising:
forming a first interconnect structure over a first substrate, wherein the first interconnect structure includes a plurality of first interconnect elements;
forming a second substrate over the first substrate such that the first interconnect structure is disposed between the first substrate and the second substrate;
forming a plurality of doped regions in the second substrate;
forming a via that extends vertically through the second substrate, wherein the via is formed to be electrically coupled to the first interconnect structure but does not extend through any of the doped regions in the second substrate;
forming a dummy gate over the second substrate, wherein the dummy gate is formed to be electrically coupled to the via; and
forming a second interconnect structure over the second substrate, the second interconnect structure including a plurality of second interconnect elements.

13. The method of claim 12 , further comprising:
forming a first circuit cell at least partially in the second substrate; and
forming a second circuit cell at least partially in the second substrate, wherein the dummy gate does not serve as a functional part of either the first circuit cell or the second circuit cell.

14. The method of claim 13 , wherein:
the first circuit cell and the second circuit cell are formed to be adjacent to each other, and wherein the dummy gate is formed to be located between the first circuit cell and the second circuit cell but not at an edge of the first circuit cell or at an edge of the second circuit cell.

15. The method of claim 12 , wherein the forming of the dummy gate comprises forming an electrically-floating gate that is not electrically tied to a power rail.

16. The method of claim 12 , wherein the forming the via and the forming the dummy gate are performed such that the dummy gate is electrically coupled to at least one of the first interconnect elements.

17. The method of claim 12 , further comprising:
forming source/drain regions in at least the second substrate; and
forming a further via that electrically extends at least partially through the second substrate and that electrically couples one of the source/drain region with one of the first interconnect elements.

18. The method of claim 12 , wherein the forming of the second interconnect structure comprises electrically coupling the dummy gate with at least one of the second interconnect elements.

19. The method of claim 12 , wherein the forming of the second substrate comprises forming the second substrate using a deposition process, and wherein the second substrate is formed to be thinner than the first substrate.

20. A method, comprising:
forming a first interconnect structure over a first substrate, wherein the first interconnect structure includes a plurality of first interconnect elements;
forming a second substrate over the first substrate such that the first interconnect structure is disposed between the first substrate and the second substrate, wherein the second substrate is formed to be thinner than the first substrate;
forming a via that extends vertically through the second substrate, wherein the via is formed to be electrically coupled to the first interconnect structure;
forming a first circuit cell at least partially in the second substrate and forming a second circuit cell at least partially in the second substrate; and
forming a dummy gate over a region of the second substrate that is disposed between the first circuit cell and the second circuit cell, wherein the dummy gate is formed to be electrically coupled to the via but not coupled with a power rail.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Guo Ta-Pen
• Diaz Carlos H
• Colinge Jean-Pierre
• Lin Yi-Hsiung

Classifications

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title