Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

Patent metadata

Field	Value
Publication number	US-9691695-B2
Application number	US-201514840364-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Aug 31, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

First claim

What is claimed is:

1. A three-dimensional Integrated Circuit (3D-IC), comprising:
a first tier device that includes: a first substrate and a first interconnect structure formed over the first substrate;
a second tier device coupled to the first tier device, wherein the second tier device includes: a second substrate, a doped region formed in the second substrate, a dummy gate formed over the second substrate, and a second interconnect structure formed over the second substrate, wherein the dummy gate is electrically floating, and wherein the dummy gate is located between two neighboring circuits of the second tier device but is not a part of either of the two circuits; and
an inter-tier via extending through the second substrate;
wherein:
the inter-tier via has a first end and a second end opposite the first end;
the first end of the inter-tier via is coupled to the first interconnect structure; and
the second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

2. The 3D-IC of claim 1 , wherein:
the second end of the inter-tier via is connected to the doped region; and
the doped region is a source/drain region.

3. The 3D-IC of claim 1 , wherein:
the second end of the inter-tier via is connected to the dummy gate.

4. The 3D-IC of claim 3 , wherein the dummy gate is located at an edge of at least one of the two neighboring circuits.

5. The 3D-IC of claim 3 , wherein:
the dummy gate is a first dummy gate; and
the second tier device further includes a second dummy gate located adjacent to the first dummy gate and between the two neighboring circuits.

6. The 3D-IC of claim 5 , wherein:
the inter-tier via is a first inter-tier via;
the 3D-IC further comprises a second inter-tier via having a first end and a second end opposite the first end;
the first end of the second inter-tier via is coupled to the first interconnect structure; and
the second end of the second inter-tier via is connected to the second dummy gate.

7. The 3D-IC of claim 6 , wherein:
the second interconnect structure includes a plurality of interconnect layers that each contain one or more metal lines; and
the second end of the inter-tier via is connected to one of the metal lines.

8. The 3D-IC of claim 7 , wherein:
the inter-tier via is a first inter-tier via;
the 3D-IC further comprises a second inter-tier via having a first end and a second end opposite the first end;
the first ends of the first inter-tier via and the second inter-tier via are each coupled to the first interconnect structure; and
the second ends of the first inter-tier via and the second inter-tier via are connected to different metal lines of the second interconnect structure.

9. The 3D-IC of claim 1 , wherein:
the second tier device includes an empty cell; and
the inter-tier via extends through the empty cell.

10. The 3D-IC of claim 1 , wherein:
the 3D-IC includes a circuit cell decomposed into a first portion and a second portion;
the first portion of the decomposed circuit cell is implemented on the first tier device;
the second portion of the decomposed circuit cell is implemented on the second tier device; and
the inter-tier via and one or more further inter-tier vias electrically interconnect the first and second portions of the decomposed circuit cell together.

11. The 3D-IC of claim 1 , wherein:
the first tier device contains an n-type transistor;
the second tier device contains a p-type transistor; and
the n-type transistor and the p-type transistor are electrically coupled together at least in part by the inter-tier via.

12. A three-dimensional Integrated Circuit (3D-IC), comprising:
a bottom tier device that includes: a bottom substrate and a bottom interconnect structure located over the bottom substrate, wherein the bottom interconnect structure includes a plurality of metal layers that each contain a plurality of metal lines;
a top tier device that includes: a top substrate, a plurality of circuit cells formed on the top substrate, a dummy gate that is not a functional part of any of the circuit cells, the dummy gate being located at an edge of one of the circuit cells and between two of the circuit cells that are adjacent to one another, and a top interconnect structure located over the top substrate, wherein the top interconnect structure includes a plurality of metal layers that each contain a plurality of metal lines, wherein the top tier device is formed over the bottom tier device; and
an inter-tier via extending through the top substrate;
wherein:
the inter-tier via has a top end and a bottom end opposite the top end;
the bottom end of the inter-tier via is connected to one of the metal lines of the bottom interconnect structure; and
the top end of the inter-tier via is connected to the dummy gate of one of the metal lines of the top interconnect structure.

13. The 3D-IC of claim 12 , wherein:
the dummy gate is a first dummy gate;
the top tier device further includes a second dummy gate located adjacent to the first dummy gate and at an edge of another one of the circuit cells;
the inter-tier via is a first inter-tier via;
the 3D-IC further comprises a second inter-tier via having a top end and a bottom end opposite the top end;
the bottom ends of the first and second inter-tier vias are both connected to the same metal line of the bottom interconnect structure; and
the top ends of the first and second inter-tier vias are connected to the first and second dummy gates, respectively.

14. The 3D-IC of claim 12 , wherein:
the inter-tier via is a first inter-tier via;
the 3D-IC further comprises a second inter-tier via having a top end and a bottom end opposite the top end;
the bottom ends of the first inter-tier via and the second inter-tier via are both connected to the same metal line of the bottom interconnect structure; and
the top ends of the first and second inter-tier vias are connected to different metal lines of the top interconnect structure, respectively.

15. The 3D-IC of claim 12 , wherein:
the top tier device includes an empty cell; and
the inter-tier via extends through the empty cell.

16. The 3D-IC of claim 12 , wherein:
one of the circuit cells is decomposed into a first segment and a second segment;
the first segment is implemented on the bottom tier device;
the second segment is implemented on the top tier device; and
the first segment and the second segment are electrically interconnected together by the inter-tier via and one or more further inter-tier vias.

17. A three-dimensional Integrated Circuit (3D-IC), comprising:
a bottom tier device that includes: a first substrate and a first interconnect structure formed over the first substrate;
a top tier device coupled to the bottom tier device, wherein the top tier device includes: a plurality of circuit cells, a second substrate, a doped region formed in the second substrate, an electrically-floating gate formed over the second substrate, and a second interconnect structure formed over the second substrate, wherein the electrically-floating gate is not electrically coupled to a power supply rail, and wherein the electrically-floating gate is located between two of the circuit cells but is not a part of the two circuit cells; and
a via extending through the second substrate;
wherein:
the via has a first end and a second end opposite the first end;
the first end of the via is coupled to the first interconnect structure; and
the second end of the via is coupled to: the doped region, the elect

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Guo Ta-Pen
• Diaz Carlos H
• Colinge Jean-Pierre
• Lin Yi-Hsiung

Classifications

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title