Semiconductor device with active pattern including a transition pattern and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-12557374-B2
Application number	US-202418736793-A
Country	US
Kind code	B2
Filing date	Jun 7, 2024
Priority date	Aug 19, 2020
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A semiconductor device including a substrate including first and second regions along a first direction, and a third region between the first region and the second region, an active pattern extending in the first direction, on the substrate, and first to third gate electrodes spaced apart from each other and extending in a second direction, on the active pattern, the active pattern of the first region including first semiconductor patterns spaced apart from each other and penetrating the first gate electrode, the active pattern of the second region including second semiconductor patterns spaced apart from each other and penetrating the second gate electrode, the active pattern of the third region including a transition pattern protruding from the substrate and intersecting the third gate electrode and including a sacrificial pattern and a third semiconductor pattern alternately stacked on the third region and including different materials from each other.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate including a first region and a second region arranged along a first direction, and a third region between the first region and the second region; an active pattern extending in the first direction, on the substrate; first to third gate structures spaced apart from each other and extending in a second direction intersecting the first direction, on the active pattern; and epitaxial patterns disposed between the first and third gate structures and between the second and the third gate structures, wherein the active pattern of the first region includes first semiconductor patterns spaced apart from each other and penetrating the first gate structure, the active pattern of the second region includes second semiconductor patterns spaced apart from each other and penetrating the second gate structure, the active pattern of the third region includes a transition pattern protruding from the substrate, the first gate structure includes first internal spacers interposed between the first semiconductor patterns, the second gate structure includes second internal spacers interposed between the second semiconductor patterns, the epitaxial patterns are in direct contact with surfaces of the transition pattern facing the first direction, and the third gate structure surrounds side surfaces and an upper surface of the transition pattern.

2 . The semiconductor device of claim 1 , wherein the transition pattern includes sacrificial patterns and third semiconductor patterns alternately stacked on the third region and including different materials from each other.

3 . The semiconductor device of claim 2 , wherein the third gate structure includes third internal spacers interposed between the third semiconductor patterns.

4 . The semiconductor device of claim 2 , wherein the epitaxial patterns are in direct contact with the third semiconductor pattern, and do not contact with the sacrificial pattern.

5 . The semiconductor device of claim 2 , the first semiconductor pattern, the second semiconductor pattern and the third semiconductor pattern include a first semiconductor material, respectively, and
the sacrificial pattern includes a second semiconductor material different from the first semiconductor material.

6 . The semiconductor device of claim 1 , wherein the transition pattern is a single material layer including a semiconductor material.

7 . The semiconductor device of claim 6 , wherein the first semiconductor pattern, the second semiconductor pattern, and the single material layer include silicon (Si).

8 . The semiconductor device of claim 1 , wherein the transition pattern includes an inclined surface which forms an acute angle with side surfaces of the third gate structure.

9 . The semiconductor device of claim 1 , wherein the first gate structure includes a first gate electrode extending in the second direction, and a gate spacer extending along a side surface of the first gate electrode, and
a thickness of the gate spacer in the first direction is as same as a thickness of the first internal spacer in the first direction.

10 . The semiconductor device of claim 1 , wherein the first gate structure includes a first gate electrode extending in the second direction, and a gate spacer extending along a side surface of the first gate electrode, and
a thickness of the gate spacer in the first direction is different from a thickness of the first internal spacer in the first direction.

11 . A semiconductor device comprising:
a substrate including a first region and a second region arranged along a first direction, and a third region between the first region and the second region; an active pattern extending in the first direction, on the substrate; first to third gate structures spaced apart from each other and extending in a second direction intersecting the first direction, on the active pattern; and epitaxial patterns disposed between the first and third gate structures and between the second and the third gate structures, wherein the active pattern of the first region includes first semiconductor patterns spaced apart from each other and penetrating the first gate structure, the active pattern of the second region includes second semiconductor patterns spaced apart from each other and penetrating the second gate structure, the active pattern of the third region includes a transition pattern protruding from the substrate, the epitaxial patterns are in direct contact with surfaces of the transition pattern facing the first direction, the third gate structure surrounds side surfaces and an upper surface of the transition pattern, and a third width of the transition pattern in the second direction is as same as a first width of the first semiconductor pattern in the second direction and a second width of the second semiconductor pattern in the second direction.

12 . The semiconductor device of claim 11 , wherein the transition pattern includes sacrificial patterns and third semiconductor patterns alternately stacked on the third region and including different materials from each other.

13 . The semiconductor device of claim 12 , the first semiconductor pattern, the second semiconductor pattern and the third semiconductor pattern include a first semiconductor material, respectively, and
the sacrificial pattern includes a second semiconductor material different from the first semiconductor material.

14 . The semiconductor device of claim 11 , wherein the transition pattern is a single material layer including a semiconductor material.

15 . The semiconductor device of claim 14 , wherein the first semiconductor pattern, the second semiconductor pattern, and the single material layer include silicon (Si).

16 . The semiconductor device of claim 11 , wherein the transition pattern includes an inclined surface which forms an acute angle with side surfaces of the third gate structure.

17 . A semiconductor device comprising:
a substrate including a first region and a second region arranged along a first direction, and a third region between the first region and the second region; a first wire pattern spaced apart from the substrate and extending in the first direction, on the first region; a second wire pattern spaced apart from the substrate and extending in the first direction, on the second region; a transition pattern protruding from the substrate and extending in the first direction, on the third region; a first epitaxial pattern directly connecting side surfaces of the first wire pattern and side surfaces of the transition pattern, between the first wire pattern and the transition pattern; and a second epitaxial pattern directly connecting side surfaces of the second wire pattern and the side surfaces of the transition pattern, between the second wire pattern and the transition pattern.

18 . The semiconductor device of claim 17 , wherein the transition pattern is a fin-type pattern.

19 . The semiconductor device of claim 17 , wherein the transition pattern includes a sacrificial pattern and a third wire pattern sequentially stacked on the third region and including materials different from each other.

20 . The semiconductor device of claim 17 wherein the transition pattern is a single material layer including a semiconductor material.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Seong-Ho
• Lee Jong Han
• Park Jong Ha
• Lee Jae Hyun
• Baek Jong Hoon
• Jeong Da Bok

Classifications

• H10D84/834 Primary

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title

• H10D84/0128 Primary

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title