Semiconductor devices having tapered active regions

Patent metadata

Field	Value
Publication number	US-9634092-B2
Application number	US-201615046455-A
Country	US
Kind code	B2
Filing date	Feb 18, 2016
Priority date	Feb 26, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Provided is a finFET device. The finFET device may include an active region which protrudes vertically from a substrate, a channel region disposed on a center of the active region, a drain region disposed on one side surface of the channel region, and a source region disposed on the other side surface of the channel region, a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section, gate spacers formed on outer surfaces of the gate insulating layer, drain spacers formed on two opposing side surfaces of the drain region, and source spacers formed on two opposing side surfaces of the source region, and at least one of the two side surfaces of the drain region has a tapered part.

First claim

What is claimed is:

1. A finFET device comprising:
an active region protruding from a substrate, wherein the active region comprises:
a channel region disposed at a center of the active region;
a drain region disposed on a first side of the channel region;
a source region disposed on a second side of the channel region opposite the first side;
a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section;
gate spacers formed on outer surfaces of the gate insulating layer;
drain spacers formed on two opposing side surfaces of the drain region; and
source spacers formed on two opposing side surfaces of the source region, and
wherein the two opposing side surfaces of the drain region are arranged so the drain region has a tapered region tapered in a direction extending away from the channel region, and
wherein a boundary between the channel region and the drain region has a same size as a boundary between the channel region and the source region.

2. The finFET device of claim 1 , wherein the tapered region of the drain region is in contact with the drain spacers.

3. The finFET device of claim 1 , wherein both of the two opposing side surfaces of the drain region have tapered parts.

4. The finFET device of claim 1 , wherein the two opposing side surfaces of the drain region are perpendicular to the substrate and a top surface of the drain region, and extend from the substrate to the top surface of the drain region, and
wherein a center surface area of at least one of the two opposing side surfaces of the drain region is planar and both end surface areas of the at least one of the two opposing side surfaces of the drain region are tapered in directions extending toward the center surface area.

5. The finFET device of claim 1 , wherein the two opposing side surfaces of the drain region are perpendicular to the substrate and a top surface of the drain region, and extend from the substrate to the top surface of the drain region, and
wherein at least one of the two opposing side surfaces of the drain region is tapered from a first end of the drain region nearest the channel region toward a central part of the drain region and tapered from a second end of the drain region farthest the channel region toward the central part of the drain region.

6. The finFET device of claim 1 , wherein part of the drain region has a concave curved surface.

7. The finFET device of claim 1 , wherein at least one of the two opposing side surfaces of the source region has a tapered part.

8. A finFET device comprising:
an active region protruding from a substrate, wherein the active region comprises:
a channel region;
a drain region disposed on a first side of the channel region in an X direction; and
a source region disposed on a second side of the channel region in the X direction; and
wherein the drain region has two side surfaces opposite in a Y direction perpendicular to the X direction, and the two side surfaces of the drain region form a first portion tapered as it extends away from the channel region and a second portion tapered as it extends toward the channel region.

9. The finFET device of claim 8 , wherein both of the two side surfaces of the drain region are tapered.

10. The finFET device of claim 8 , wherein at least a first side surface of the drain region is tapered from both ends of the drain region to a central part of the drain region.

11. The finFET device of claim 10 , wherein the central part of the first side surface of the drain region is planar.

12. The finFET device of claim 8 , wherein the source region has two side surfaces opposite in the Y direction, and a first of the two side surfaces of the source region is tapered.

13. The finFET device of claim 12 , wherein the first side surface of the source region is tapered from both ends of the source region to a central part of the source region.

14. The finFET device of claim 13 , wherein the central part of the first side surface of the source region is planar.

15. The finFET device of claim 8 , wherein both of the two side surfaces of the source region are tapered.

16. The finFET device of claim 8 , wherein at least a first side surface of the source region is tapered from both ends of the drain region to a central part of the drain region.

17. The finFET device of claim 16 , wherein the central part of the first side surface of the source region is planar.

18. A nanowire FET device comprising:
a first SiGe bulk body formed on a substrate, wherein conductive impurities are implanted into the first SiGe bulk body and the first SiGe bulk body is provided as a drain region;
a gate pattern horizontally spaced apart from the first SiGe bulk body;
a second SiGe bulk body horizontally spaced apart from the gate pattern, wherein conductive impurities are implanted into the second SiGe bulk body and the second SiGe bulk body is provided as a source region; and
one or more nanowires which horizontally pass through the first SiGe bulk body, the gate pattern, and the second SiGe bulk body,
wherein the nanowire includes a drain region which horizontally passes through the first SiGe bulk body, a channel region which passes through the gate pattern, and a source region which passes through the second SiGe bulk body, and wherein the drain region of the nanowire has a tapered surface, and
wherein the drain region of the nanowire is tapered from the channel region to an end.

19. A nanowire FET device of claim 18 , wherein the drain region of the nanowire has a concave tapered surface.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Bhuwalka Krishna Kumar
• Wu Zhenhua
• Kwon Uihui
• Lee keunho

Classifications

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H01L29/0673 Primary

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic