Forming horizontal bipolar junction transistor compatible with nanosheets

Patent metadata

Field	Value
Publication number	US-10269790-B2
Application number	US-201815933768-A
Country	US
Kind code	B2
Filing date	Mar 23, 2018
Priority date	Mar 9, 2017
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate. The gate includes a nanosheet extending through a channel region of the gate. The FET includes a pair of source/drains arranged on opposing sides of the gate. The semiconductor device further includes a bipolar junction transistor (BJT) arranged adjacent to the FET on the substrate. The BJT includes an emitter and a collector. The BJT includes a nanosheet including a semiconductor material extending from the emitter to the collector, with a doped semiconductor material arranged above and below the nanosheet.

First claim

What is claimed is:

1. A method of forming a field effect transistor (FET) and a bipolar junction transistor (BJT) on a common substrate, the method comprising:
forming a first nanosheet stack in a FET region and a second nanosheet stack in a BJT region of the common substrate;
forming a first dummy gate on the first nanosheet stack and a second dummy gate on the second nanosheet stack;
depositing a semiconductor material on opposing sides of the first dummy gate and the second dummy gate;
removing a first nanosheet from each of the first nanosheet stack and the second nanosheet stack;
removing the second dummy gate in the BJT region; and
depositing doped semiconductor material on and around the second nanosheet of the BJT region.

2. The method of claim 1 , wherein depositing the semiconductor material comprises performing an epitaxial growth process.

3. The method of claim 1 , wherein the semiconductor material comprises n-type doped semiconductor material.

4. The method of claim 1 , wherein a width of the second dummy gate of the BJT is greater than a width of the first dummy gate of the FET.

5. The method of claim 1 , wherein the first nanosheet comprises silicon.

6. The method of claim 5 , wherein the first nanosheet alternates with a second nanosheet comprising silicon germanium.

7. The method of claim 1 further comprising depositing a mask on the FET region before removing the second dummy gate from the BJT region.

8. The method of claim 1 , wherein the doped semiconductor material comprises epitaxially grown semiconductor material.

9. The method of claim 8 , wherein the epitaxially grown semiconductor material comprises a p-type dopant.

10. The method of claim 1 , wherein the semiconductor material deposited on the second dummy gate forms the emitter and the collector of the BJT region.

11. The method of claim 10 , wherein the semiconductor material comprises an n-type dopant.

12. The method of claim 1 , wherein the first dummy gate and the second dummy gate each comprise gate spacers.

13. The method of claim 12 , wherein removing the first nanosheet comprises a selective etch process that results in a second nanosheet remaining suspended between the gate spacers.

14. The method of claim 1 further comprising removing the first dummy gate prior to removing the first nanosheet.

15. The method of claim 14 further comprising replacing sacrificial material of the first dummy gate with a metal gate stack.

16. The method of claim 15 , wherein the metal gate stack comprises a dielectric layer and a conductive metal.

17. The method of claim 1 , wherein the BJT has an N-P junction and a P-N junction.

18. A semiconductor device, comprising:
a field effect transistor (FET) comprising a nanosheet extending through a channel region of a gate; and
a bipolar junction transistor (BJT) comprising a nanosheet comprising a semiconductor material extending from an emitter to a collector.

19. The semiconductor device of claim 18 , wherein the FET further comprises a pair of source/drains comprising an epitaxial semiconductor material on opposing sides of the gate.

20. The semiconductor device of claim 18 , wherein the BJT further comprises a doped semiconductor material arranged above and below the nanosheet.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Li Juntao
• Wang Geng
• Zhang Qintao

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L29/165

  Electricity · mapped topic

• H01L29/6625

  Electricity · mapped topic

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/66265

  Electricity · mapped topic