Method of forming integrated circuit with gate-all-around field effect transistor and the resulting structure

Patent metadata

Field	Value
Publication number	US-10431663-B2
Application number	US-201815867036-A
Country	US
Kind code	B2
Filing date	Jan 10, 2018
Priority date	Jan 10, 2018
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.

First claim

What is claimed is:

1. A method comprising:
providing a substrate;
forming a semiconductor fin on the substrate, wherein the semiconductor fin has a first width; and
forming a first transistor using the semiconductor fin, the forming of the first transistor comprising:
forming a sacrificial gate on a first portion of the semiconductor fin such that second portions of the semiconductor fin extend laterally beyond the sacrificial gate;
forming a sidewall spacer comprising a gate section on the sacrificial gate and fin sections on the second portions of the semiconductor fin;
removing the second portions of the semiconductor fin to create source/drain openings and to expose vertical surfaces of the first portion of the semiconductor fin;
widening the source/drain openings such that the widened source/drain openings have a second width that is greater than the first width of the semiconductor fin, wherein the first width of the semiconductor fin and the second width of the widened source/drain openings are measured in a same direction; and
after the widening of the source/drain openings, forming source/drain regions in the widened source/drain openings.

2. The method of claim 1 ,
wherein the substrate comprises a first semiconductor material,
wherein the forming of the semiconductor fin comprises forming a multi-layer semiconductor fin comprising alternating layers of a second semiconductor material and the first semiconductor material,
wherein the removing of the second portions of the semiconductor fin exposes vertical surfaces of the first semiconductor material and the second semiconductor material, and
wherein the forming of the first transistor further comprises:
after the widening of the source/drain openings and before the forming of the source/drain regions, etching exposed surfaces of the second semiconductor material to form cavities in the first portion of the semiconductor fin;
conformally depositing an isolation layer so that the isolation layer fills the cavities and is within the widened source/drain openings; and
selectively and isotropically etching the isolation layer, wherein the etching of the isolation layer is performed until the isolation layer is completely removed from the widened source/drain openings and stopped prior to removal of the isolation layer from the cavities such that isolation elements remain in the cavities.

3. The method of claim 2 ,
wherein the forming of the sidewall spacer comprises:
conformally depositing a first spacer layer;
selectively and anisotropically etching the first spacer layer to remove horizontal portions of the first spacer layer;
after the selectively and anisotropically etching of the first spacer layer, conformally depositing a second spacer layer; and
selectively and anisotropically etching the second spacer layer to remove horizontal portions of the second spacer layer so as to form a multi-layer sidewall spacer and expose top surfaces of the second portions of the semiconductor fin,

wherein the forming of the first transistor further comprises forming a first layer of interlayer dielectric material adjacent to the multi-layer sidewall spacer such that top surfaces of the fin sections are at or below a level of a top surface of the first layer of interlayer dielectric material,
wherein the first spacer layer, the second spacer layer and the first layer of interlayer dielectric material comprise different dielectric materials, and
wherein the widening of the source/drain openings comprises:
selectively and isotropically etching the second spacer layer such that the second spacer layer is completely removed from the source/drain openings without exposing the sacrificial gate; and
selectively and isotropically etching the first spacer layer such that the first spacer layer is completely removed.

4. The method of claim 3 , wherein the first spacer layer is thicker than the second spacer layer.

5. The method of claim 3 , wherein the forming of the first transistor further comprises:
after the forming of the source/drain regions, depositing an etch stop layer over the first layer of interlayer dielectric material, the source/drain regions, and the sacrificial gate;
depositing a second layer of interlayer dielectric material on the etch stop layer;
performing a polishing process to expose the sacrificial gate;
selectively removing the sacrificial gate and the second semiconductor material to form a gate opening;
forming a replacement metal gate with a dielectric gate cap in the gate opening;
forming contact openings that extend through the second layer of the interlayer dielectric material and through the etch stop layer to the source/drain regions; and
forming contacts in the contact openings.

6. The method of claim 5 , wherein the contact openings are formed so as to further extend into the first layer of interlayer dielectric material to expose top and side surfaces of the source/drain regions and wherein the forming of the contacts further comprises forming the contacts in the contact openings adjacent to the top and side surfaces of the source/drain regions.

7. The method of claim 6 ,
wherein the forming of the source/drain regions in the widened source/drain openings comprises depositing epitaxial semiconductor material so as to overfill the widened source/drain openings, and
wherein the method further comprises selectively and isotropically etching the epitaxial semiconductor material so that upper portions of the source/drain regions that extend above the widened source/drain openings are narrower than lower portions of the source/drain regions within the widened source/drain openings.

8. The method of claim 1 ,
wherein the forming of the sidewall spacer comprises:
conformally depositing a spacer layer; and
performing an anisotropic etch process to remove horizontal portions of the spacer layer in order to form the sidewall spacer,

wherein the anisotropic etch process exposes top surfaces of the second portions of the semiconductor fin, and
wherein the widening of the source/drain openings comprises selectively and isotropically etching the spacer layer such that a top surface and one side surface of the gate section are etched without exposing the sacrificial gate and such that top surfaces and opposing side surfaces of the fin sections are etched.

9. The method of claim 1 , further comprising, during the forming of the first transistor, concurrently forming any of a second transistor and a third transistor, wherein the first transistor comprises a nanowire-type field effect transistor, the second transistor comprises nanosheet-type field effect transistor, and the third transistor comprises a fin-type field effect transistor.

10. A method comprising:
providing a semiconductor substrate;
forming at least one semiconductor fin on the semiconductor substrate; and
forming a first transistor using the semiconductor fin, the forming of the first transistor comprising:
forming a sacrificial gate with a sacrificial gate cap on a first portion of the semiconductor fin such that second portions of the semiconductor fin extend laterally beyond the sacrificial gate;
forming a sidewall spacer comprising a gate section on sidewalls of the sacrificial gate and fin sections on sidewalls of the second portions of the semiconductor fin;
forming a protective cap on a top surface of the gate section only of the sidewall spacer such that top surfaces of the fin sections of the sidewall spacer are exposed;
after the forming of the protective cap, removing the fin sections of the sidewall spacer;
removing the second portions of the semiconductor fin such that opposing sides of the first portion of the semicon

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Pranatharthiharan Balasubramanian
• Montanini Pietro
• Frougier Julien

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title